Next gen Zen 2/3 "Starship" and derivatives

[wahdangun]

Doesn't match up with the work put into Pinnacle Ridge on other fronts. Cache latencies got tightened, IF latencies got tightened, memory controller is entirely different (don't ask me how I know that ), branch prediction got updated, and 12nm LP requires you to recompile and optimize the design either way. You can't just copy paste the design, even if it's lower effort than moving to a different node.

Whatever cell density they choose, it wasn't done for the sake of design cost savings, but rather what they think will be best for them in terms of die size/performance. Otherwise they'd just use GloFo's matured 14nm process.

So if IMC is different then can we expect it to work with 3600 or more, ram kit ?

With support ram above 3200 and faster and tighter IF, then the ipc can gain more than 15%

 

[exquisitechar]

Doesn't match up with the work put into Pinnacle Ridge on other fronts. Cache latencies got tightened, IF latencies got tightened, memory controller is entirely different (don't ask me how I know that ), branch prediction got updated, and 12nm LP requires you to recompile and optimize the design either way. You can't just copy paste the design, even if it's lower effort than moving to a different node.

Whatever cell density they choose, it wasn't done for the sake of design cost savings, but rather what they think will be best for them in terms of die size/performance. Otherwise they'd just use GloFo's matured 14nm process.

I'll take your word for it.

The Ryzen 2000 series is looking rather promising. I think the recent GB leak, presumably featuring a Ryzen 2600 QS, paints a pretty picture as well, even though gathering accurate data from it is difficult.

 

[raghu78]

Doesn't match up with the work put into Pinnacle Ridge on other fronts. Cache latencies got tightened, IF latencies got tightened, memory controller is entirely different (don't ask me how I know that ), branch prediction got updated, and 12nm LP requires you to recompile and optimize the design either way. You can't just copy paste the design, even if it's lower effort than moving to a different node.

Whatever cell density they choose, it wasn't done for the sake of design cost savings, but rather what they think will be best for them in terms of die size/performance. Otherwise they'd just use GloFo's matured 14nm process.

Nice. Looks like PR will significantly improve memory and cache latency benefiting games and other workloads which are memory latency sensitive. The IMC looks to have got a major revamp to bring a host of improvements like broader compatibility with DDR4 DRAM, higher DDR4 DRAM speed support and improved memory latency. I am excited and look forward to PR launch. Mark Papermaster said back when Zen launched that it was tock tock tock. I think the overall improvements in ST and MT perf (clocks + IPC) are going to be worthy of Zen+ being called a tock.

https://www.pcworld.com/article/315...hitecture-is-expected-to-last-four-years.html

When asked how long Zen would last, compared to Intel’s two-year tick-tock cadence, Papermaster confirmed the four-year lifespan and tapped the table in front of him: “We’re not going tick-tock,” he said. “Zen is going to be tock, tock, tock.”

 

[NostaSeronx]

Otherwise they'd just use GloFo's matured 14nm process.

12LP can be used as a mature 14nm process.

So, rather than use the 14nm+ with Raven Ridge. AMD switched it to 12LP to get an extra 10% of performance over that process. While, most of the design from Zeppelin could be reused regardless of 14nm, 14nm+ and 12nm(as 14nm++ or 14nm HP).

14nm -> Summit
14nm+ -> Raven
14nm++ by 12LP -> Pinnacle and Picasso, etc.

 

[CatMerc]

So if IMC is different then can we expect it to work with 3600 or more, ram kit ?

With support ram above 3200 and faster and tighter IF, then the ipc can gain more than 15%

Yup. If what I've heard is correct, 4000MHz for the really good kits and CPU's could be possible. Might just be for benchmarking runs and not 24/7 stable though.

12LP can be used as a mature 14nm process.

So, rather than use the 14nm+ with Raven Ridge. AMD switched it to 12LP to get an extra 10% of performance over that process. While, most of the design from Zeppelin could be reused regardless of 14nm, 14nm+ and 12nm(as 14nm++ or 14nm HP).

14nm -> Summit
14nm+ -> Raven
14nm++ by 12LP -> Pinnacle and Picasso, etc.

You can't just copy paste a design to a node with a shrinked BEOL. At that point you might as well tweak things while rebuilding it.

 

[Atari2600]

You can't just copy paste a design to a node with a shrinked BEOL. At that point you might as well tweak things while rebuilding it.

Yep. It'd make no sense to do the bare minimum required to port the design over. It would be highly sub-optimal compared to what you could achieve.

 

[raghu78]

Yup. If what I've heard is correct, 4000MHz for the really good kits and CPU's could be possible. Might just be for benchmarking runs and not 24/7 stable though.

You can't just copy paste a design to a node with a shrinked BEOL. At that point you might as well tweak things while rebuilding it.

Well said. We already have AMD confirming higher clocks, silicon improvements for cache and memory speed and latency and improved precision boost. These are all not coming without significant design effort.

https://www.computerbase.de/2018-01/amd-ryzen-threadripper-2000/

James Prior said in an interview at CES 2018 that DDR4 4000 should be achievable with Samsung B die on the 400 series chipsets and Ryzen 2000 series desktop CPUs.

https://www.youtube.com/watch?v=CZOIOX-Ncr0

 

[The Stilt]

James Prior said in an interview at CES 2018 that DDR4 4000 should be achievable with Samsung B die on the 400 series chipsets and Ryzen 2000 series desktop CPUs.

https://www.youtube.com/watch?v=CZOIOX-Ncr0

He did no such thing.

Q: ...How about putting faster ram in, you could say what about those 4000 (MHz) RAM bars (modules) putting those guys in?

A: Yeah, we're really excited, hopefully on the new 400-series chipset motherboards you'll be able to get really easy 4000MHz speeds probably with the Samsung B-die memory kit...

 

[Kenmitch]

He did no such thing.

Q: ...How about putting faster ram in, you could say what about those 4000 (MHz) RAM bars (modules) putting those guys in?

A: Yeah, we're really excited, hopefully on the new 400-series chipset motherboards you'll be able to get really easy 4000MHz speeds probably with the Samsung B-die memory kit...

Should be and hopefully pretty much the same thing in the end....More like a we'll see in the end.

I'm leaning towards the MB makers didn't really didn't give it a whole lot of effort as they most likely like users here predicted AMDs future products by their past performance.

 

[The Stilt]

Should be and hopefully pretty much the same thing in the end....More like a we'll see in the end.

I'm leaning towards the MB makers didn't really didn't give it a whole lot of effort as they most likely like users here predicted AMDs future products by their past performance.

Yes, we'll see.

However are you suggesting that the memory clocks on current gen. Ryzen products are limited by the motherboard designs?

 

[Kenmitch]

Yes, we'll see.

However are you suggesting that the memory clocks on current gen. Ryzen products are limited by the motherboard designs?

Nope....Just that if AMD is from this point taken seriously that more time, energy, resources, etc. will be used in designing MB's for their offerings.

 

[thigobr]

Probably not above 3600 MHz where the IF clock limitations come into play but a lot of boards have a really hard time crossing the 3200 MHz barrier...
E.g. Asus Prime X370 Pro

 

[raghu78]

He did no such thing.

Q: ...How about putting faster ram in, you could say what about those 4000 (MHz) RAM bars (modules) putting those guys in?

A: Yeah, we're really excited, hopefully on the new 400-series chipset motherboards you'll be able to get really easy 4000MHz speeds probably with the Samsung B-die memory kit...

AMD has made silicon level improvements in Pinnacle Ridge for higher memory speeds, improved memory and cache latency. What more confirmation do you want that AMD has made significant improvements to the IMC and will have broader memory compatibility and better support for higher DDR4 speeds ?

Sent from my SM-G935V using Tapatalk

 

[IEC]

AMD has made silicon level improvements in Pinnacle Ridge for higher memory speeds, improved memory and cache latency. What more confirmation do you want that AMD has made significant improvements to the IMC and will have broader memory compatibility and better support for higher DDR4 speeds ?

Sent from my SM-G935V using Tapatalk

You are inferring improvements that may or may not have made it to the final product based on a single interview. It's quite likely there are improvements, but how much remains to be seen.

P.S. Remove the Tapatalk from your sig/mobile device, it is verboten here.

 

[The Stilt]

What more confirmation do you want that AMD has made significant improvements to the IMC and will have broader memory compatibility and better support for higher DDR4 speeds ?

Actual independent reviews confirming the said changes.

 

[raghu78]

You are inferring improvements that may or may not have made it to the final product based on a single interview. It's quite likely there are improvements, but how much remains to be seen.

P.S. Remove the Tapatalk from your sig/mobile device, it is verboten here.

Fair enough. Made changes to remove signature.

 

[wahdangun]

Yes, we'll see.

However are you suggesting that the memory clocks on current gen. Ryzen products are limited by the motherboard designs?

up to 3200 it won't matter, but above that, I'm expecting its need good design.

 

[Gideon]

Actual independent reviews confirming the said changes.

Exactly. They also mentioned improved memory compatibility with Raven Ridge. And while it is a tad better, it definitely wasn't quite what I expected.

 

[itsmydamnation]

Exactly. They also mentioned improved memory compatibility with Raven Ridge. And while it is a tad better, it definitely wasn't quite what I expected.

Actual independent reviews confirming the said changes.

NO, NO NO NO NO
https://www.youtube.com/watch?v=ILYqo47M73E

 

[krumme]

Ehh i seem to remember the current imc is not made by amd but outsourced ....? Rambus??
Then one can guess the new one is made inhouse and the current was outsourced due to ttm constraints or just lack of inhouse at that time.

Didnt amd publicly confirm the imc is new? I sort of assumed that but cant remember where i got the idea from.

 

[CatMerc]

Ehh i seem to remember the current imc is not made by amd but outsourced ....? Rambus??
Then one can guess the new one is made inhouse and the current was outsourced due to ttm constraints or just lack of inhouse at that time.

Didnt amd publicly confirm the imc is new? I sort of assumed that but cant remember where i got the idea from.

The current IMC is in house.

 

[Abwx]

Methink it s from Synopsys, but it could well have been designed by former AMD empyees who were transfered to Synopsys at the time.

Dunno if it was some kind of arrangement, because if ever AMD gain significant marketshare they ll need to hire again such people...

https://www.synopsys.com/dw/ipdir.php?ds=dwc_ddr_universal_umctl2

 

[krumme]

Methink it s from Synopsys, but it could well have been designed by former AMD empyees who were transfered to Synopsys at the time.

Dunno if it was some kind of arrangement, because if ever AMD gain significant marketshare they ll need to hire again such people...

https://www.synopsys.com/dw/ipdir.php?ds=dwc_ddr_universal_umctl2

There seems to be a lot of Synopsys IP for the ddr hpy in the ryzen
"“To deliver our complex and high-performance Ryzen and EPYC SoCs on
schedule, we relied on Synopsys’ high-quality IP. Choosing DesignWare IP
with custom features and capabilities enabled us to hit our schedule and
supported our roadmap.”—Rolands Ezers, Sr. Director, I/O & Circuit Technology, AMD"

https://www.google.dk/url?sa=t&sour...FjABegQIBxAB&usg=AOvVaw2227cAPJGJabQLNZxQknkk

So yes it seems the prior solution was made due to ttm constraints.

 

[itsmydamnation]

There seems to be a lot of Synopsys IP for the ddr hpy in the ryzen
"“To deliver our complex and high-performance Ryzen and EPYC SoCs on
schedule, we relied on Synopsys’ high-quality IP. Choosing DesignWare IP
with custom features and capabilities enabled us to hit our schedule and
supported our roadmap.”—Rolands Ezers, Sr. Director, I/O & Circuit Technology, AMD"

https://www.google.dk/url?sa=t&sour...FjABegQIBxAB&usg=AOvVaw2227cAPJGJabQLNZxQknkk

So yes it seems the prior solution was made due to ttm constraints.

Designware IP is 12G SERDES that provide PCI-E, 10Gbase-x , SATA, xGMI, etc . Not the DDR interfaces, it even says it in your own link. Im makes sense to keep using synopsys for that kind of stuff, next step would be 25G SERDES.

 

[krumme]

Designware IP is 12G SERDES that provide PCI-E, 10Gbase-x , SATA, xGMI, etc . Not the DDR interfaces, it even says it in your own link. Im makes sense to keep using synopsys for that kind of stuff, next step would be 25G SERDES.

Ok then why:
"“The Synopsys DesignWare DDR4/3 PHY is a world-class
product.”– Rolands Ezers, Sr. Director, I/O & Circuit Technology, AMD"
??

And
"By licensing proven Foundation, DDR4, USB 3.0, PCIe 3.1, and Ethernet IP
from Synopsys, we are able to focus our valuable engineering resources on ongoing product differentiation.”