- Feb 8, 2001
- 8,968
- 16
- 81
One package, 8 dies (isn't each die dual-cored?), 144 MB of cache... drool!
Pic
*UPDATE*
The details
- 4 CPU dies * 2 cores/die * 2-way SMT = 16 logical CPUs per MCM
- Each core gets 20+ GBps memory bandwidth
- 4*36 MB L3 cache, each connected to a CPU die via a 1 GHz, 256-bit bus delivering an estimated 32 GBps throughput (separately from the memory bus)
- We're talking over 250 GBps can be moved over the MCM at any one time
- Expect to see 8-channel DDR memory interface = 25.6 GBps using DDR400 w/ECC
- On chip memory controllers a-la Athlon64/FX/Opteron
- 2 MCMs can be combined into a "book" connected via a half speed link
- Up to 8 MCMs can be put into one SMP machine, delivering a 64 core "Squadron" with 128 logical processors. I'll take 4 of these, please.
Pic
*UPDATE*
The details
- 4 CPU dies * 2 cores/die * 2-way SMT = 16 logical CPUs per MCM
- Each core gets 20+ GBps memory bandwidth
- 4*36 MB L3 cache, each connected to a CPU die via a 1 GHz, 256-bit bus delivering an estimated 32 GBps throughput (separately from the memory bus)
- We're talking over 250 GBps can be moved over the MCM at any one time
- Expect to see 8-channel DDR memory interface = 25.6 GBps using DDR400 w/ECC
- On chip memory controllers a-la Athlon64/FX/Opteron
- 2 MCMs can be combined into a "book" connected via a half speed link
- Up to 8 MCMs can be put into one SMP machine, delivering a 64 core "Squadron" with 128 logical processors. I'll take 4 of these, please.