They really are not good at doing this sort of things.
Thermals are a challenge there.
They really are not good at doing this sort of things.they can decrease the cost by putting only the GPCs on N2 and the rest on a cheaper node
Thermals are a challenge there.They'd want to use A16 with backside power delivery that should benefit GPUs,
If they can do 575W in 2 slots now...Thermals are a challenge there.
Not this kind of thermals.If they can do 575W in 2 slots now...
Well, we are not talking about MI300 level chip here - they just need to beat 5090 by 30-40% in raster and be at least as good with RT stuff, ideally - better.Try looking at MI300 heatmap
Yeah we do, you're putting a ton of stuff on top that has less than idea thermal resistance.Well, we are not talking about MI300 level chip here
Are you referring to 3D cache that I think is under mem controllers on MI300 or something else?you're putting a ton of stuff on top
no, BSPDN wafer itself is a chungus thermal resistance adder.Are you referring to 3D cache that I think is under mem controllers on MI300 or something else?
Ok, maybe that won't be great, but new transistors should help a fair bit by the time they are 2nd gen. Either way - this affects both AMD and NVIDIA so it's the chance for AMD to catch upBSPDN
You might be right that it's fake, but the numbers cannot be achieved with a 4090 and the cards are out there already. I think reviews will be out in a day or two anyway.Suuuure. Never shows any actual cards and has 9070 XT benchmarks available. Definitely legit.
Why miss? If it's the same process node, and based solely on SM count, +33% alone consume 33% more power. TDP in turn increased by 27%. This 6% difference is not that far from the 8% clock deficit, given some contribution from the remaining bulged IPs.It just smells of an fmax miss.
Why miss? If it's the same process node
Because when you streamline the SM, you expect to win something on fmax.Why miss?
We're not talking 202 here.If it's the same process node, and based solely on SM count, +33% alone consume 33% more power. TDP in turn increased by 27%
We're not talking 202 here.
Clock bump for every die sucks, NV bumped the power up too.How's that relevant?
When you have a streamlined SM and moar TBP you expect a not quite insignificant fmax bump. Simple as.How's that relevant?
How's that different between the 202 sku and the rest?Clock bump for every die sucks, NV bumped the power up too.
I don't know what "streamlined" means, but don't physics laws suggests otherwise, i.e. the dynamic power linearly increases with switching capacity at the same clocks?When you have a streamlined SM and moar TBP you expect a not quite insignificant fmax bump. Simple as.
The rest have no SM count bump.How's that different between the 202 sku and the rest?
Exactly what it says on the box. It's a simpler SM.I don't know what "streamlined" means
how are laws of physics related to logic or microarch designbut don't physics laws suggests otherwise, i.e. the dynamic power linearly increases with switching capacity at the same clocks?
The transistor count did teaser that already. Beside of more SMs, wider memory interface, enhanced Tensor and RT Cores and very likely 128MB L2$ the transistor count did not increase as if it would with a simply upscaled Ada chip.Exactly what it says on the box. It's a simpler SM.
Wow with those prices they must be faster than I thought 🤔AIB prices look insane and FE cards will be unicorns.