Wait for IDC to get some graphs and drop some knowledge bombs. I'm fairly sure there have been yield over time graphs floating around.
The main issue with saying what "yields" are, is defining yield.
You could say that the GTX580 die has X yield, but the yield increases if you include the GTX570.
If you then go forwards in time, retrospectively the yield increases when you add the GTX560 448-core in, since that uses the same chips.
TSMC's 40nm yields were below 60%, which is pretty bad, but not dire, and as mentioned, it depends on how you define yield. When TSMC talks about yield, their definition is going to be different to NV/AMD, because of their wide customer base who may not be able to harvest defective dies so easily.
http://www.xbitlabs.com/news/other/...SMC_s_40nm_Yields_Improved_to_60_Company.html
Yeah, what folks have to keep in mind (or become aware of) is that there are two general types of yields - Parametric Yield and Functional Yield.
Functional yield is your basic "does the chip power up? does it do math correctly? (1+1=2? or does 1+1=3?)"
This type of yield is heavily dependent on the defect density in the fab (how many "killer" particles are falling onto the wafers while the wafers are in the fab). It is the type of yield that starts out really bad and then improves as the node matures.
Forgive me for recycling this graph from 2 yrs ago, but its already prepared and in my photobucket account so we'll use it here to speak to:
In terms of functional yield, if Kepler is much larger than AMD's GPU or qualcomm's other chips being made on 28nm then it would be of no surprise to hear that Kepler yields were problematic while everyone elses yields were OK.
The second yield type is
Parametric yield. This is the yield that is based on clockspeed binning, power-consumption binning, and reliability binning.
The chip might function just fine but it can't clock over 500MHz, or it can clock just fine but it consumes 500W of power. All sorts of electrical issues can come into play which limit parametric yield.
If TSMC was having parametric yield issues you would expect it to impact all customers.
Final yield is the product of functional yield and parametric yield.
Based on the general statements made by NV, and the anecdotal observations of other 28nm customers not citing yield as a problem, I am inclined to believed the issue is simply one of functional yield (big die = lower yield).
Which, if true, means we should not expect a Fermi 2.0 in terms of power-consumption (a parametric yield issue), but maybe a Fermi 2.0 in terms of scheduling slips for functional yield enhancement purposes,