Nvidia reveals Specifications of GT300

[Kuzi]

Originally posted by: Idontcare
ATI HD4770 is 826m xtors packed into 137 mm^2.

At that xtor density, 2.4B xtors could be packed into a 398 mm^2 die.

Seems feasible to me based on the existing data.

True, but ATI and NV GPU are not directly comparable. ATI seems to get better density/efficiency from their architecture, at least for the current generation.

If we take the GT200b as an example, it has 1.4B transistors with a die size of 470 mm^2 @ 55nm.

Adding 1B more transistors (71% increase) would get us a size of about 800 mm^2 at the same process. Now going from 55 nm to 40 nm is 37% smaller, so 800*0.63 ~ 500 mm^2

So if true that the GT300 will have 2.4.B transistors, it's size should be around 500 mm^2, maybe a bit larger or a bit smaller.

I believe it's very possible NV added that many transistors to the GT300, they have to do it to get a nice jump in performance.

 

[AzN]

Originally posted by: lopri

Originally posted by: Azn
Not to mention 4870 isn't even all that much faster over 4850 with nearly 2x the bandwidth. Majority of bandwidth on 4870 is going to waste. 60gb/s is sufficient for a GPU like RV7xx series. A good 80gb/s should be more than plenty. 4770 does so well compared to 4850 and 4830 because of clock speeds not bandwidth anyway.

It would have been more cost efficient/performance pleasing if AMD added more SP and TMU instead of adding 256bit bus proposed by yacoub.

RV770 is actually the first thing I've seen that reaps such a massive gain from increased bandwidth. The only difference between HD 4850 and HD 4870 is memory being used, and thus it alone brings 20~30% performance increase at least. I mean, we don't normally expect such a dramatic difference by upgrading memory.

That's why I wondered in the past why NV hadn't mated G92 with GDDR5. Because G92 looked like an ideal candidate for a similar case. (like RV770)

If GT300 is really 512-bit using GDDR5.. That'll be a monster, for sure.

20-30% huh? Did you even account for 4870 @ 750mhz core and 4850 @ 625mhz? That 20-30% suddenly shrinks to 10-20% if that with 2x more bandwidth.

Bandwidth does bring minimum frame rates up and AA application but it literally does nothing for average frame rates or peak rates. Now if you have a huge imbalance of fillrate and bandwidth then that bandwidth does help quite a bit to bring up average frame rates...

G92 had a huge imbalance far as fillrate and bandwidth. I too think G92 would have been able to compete with 4870 or GTX260 if it had more bandwidth. RV770 is different. 4870 seems to be wasting bandwidth quite a bit while 4850 seems more balanced by looking at 4870 overclocking articles where increasing memory clocks had no impact on performance.

GT300 with 512bit and gddr5 seems far fetched and probably useless as 2900xt with 512bit memory bus not to mention the cost and sheer size associated with building such chip.

 

[Idontcare]

Originally posted by: Kuzi

Originally posted by: Idontcare
ATI HD4770 is 826m xtors packed into 137 mm^2.

At that xtor density, 2.4B xtors could be packed into a 398 mm^2 die.

Seems feasible to me based on the existing data.

True, but ATI and NV GPU are not directly comparable. ATI seems to get better density/efficiency from their architecture, at least for the current generation.

If we take the GT200b as an example, it has 1.4B transistors with a die size of 470 mm^2 @ 55nm.

Adding 1B more transistors (71% increase) would get us a size of about 800 mm^2 at the same process. Now going from 55 nm to 40 nm is 37% smaller, so 800*0.63 ~ 500 mm^2

So if true that the GT300 will have 2.4.B transistors, it's size should be around 500 mm^2, maybe a bit larger or a bit smaller.

I believe it's very possible NV added that many transistors to the GT300, they have to do it to get a nice jump in performance.

Originally posted by: thilan29
nVidia's transistor density is lower IIRC in the GT200 so they'd have to work on that to get that ~400mm^2 size.

I didn't say NV would produce the GT300 w/2.4B xtors at <400mm^2.

I said someone could, if they so wanted to, pack at least 2.4B xtors inside 400mm^2 on TSMC's 40nm.

Now had the math worked out such that it at ATI's proven xtor density it would require a 2000mm^2 die to put 2.4B xtors onto a single IC then I would have posted that information and concluded with Crieg that it is physically impossible. The maximum shot-size (field of exposure for the scanner) is on the order 1000 mm^2, if you need >1000mm^2 to pack in all your xtors (at any yield) onto a single monolithic IC you simply can't do it with today's technology on a leading-edge node.

However ATI proves it is feasible to put 2.4B xtors onto a monolithic IC given the xtor density they arrived at for their 40nm-based chips, not that doing it would necessarily be desirable or to the maximum benefit of all other designer/layout metrics of success, merely that it is feasible (the word I intentionally elected to employ in my post) based on known physical constraints and boundary conditions of the underlying manufacturing technology.

I was merely pointing out that it was not entirely out of the question as was originally implied in the post I quoted.

A comment regarding xtor density...many folks (I have gathered) are unawares that xtors have varying width and length even within the same process technology. Depending on what the circuits themselves are doing (in terms of raw TTL) the length and width of the xtors will vary from circuit to circuit on the chip. Some will be really tiny xtors, as tiny as the process technology allows (this is usually your sram xtors), and others will be huge micron-sized gargantuan xtors designed to really push the amps when turned on and be a solid resistor when turned off (I/O xtors, etc).

Using xtor count and density metrics for comparing architectures is a kinda flimsy analysis if there aren't some other boundary conditions taken into account, like solely using GHz to compare GPU's or solely using power consumption to make comparisons. Xtor density can be useful in making some loose comparison and helps assist in communicating ideas and concepts effectively in forums and the like, but its not a hard/fast metric of success so don't get too hung up on it.

 

[Genx87]

Originally posted by: thilan29
Some more info (2.4billion transistors apparently):
http://www.hardware-infos.com/...hp?news=2944&sprache=1

Interesting that it will be smaller than the original GT200. I'd suspect power numbers should be similar as well but performance should be way up.

 

[Kuzi]

Originally posted by: Idontcare
I didn't say NV would produce the GT300 w/2.4B xtors at <400mm^2.

I said someone could, if they so wanted to, pack at least 2.4B xtors inside 400mm^2 on TSMC's 40nm.

Now had the math worked out such that it at ATI's proven xtor density it would require a 2000mm^2 die to put 2.4B xtors onto a single IC then I would have posted that information and concluded with Crieg that it is physically impossible. The maximum shot-size (field of exposure for the scanner) is on the order 1000 mm^2, if you need >1000mm^2 to pack in all your xtors (at any yield) onto a single monolithic IC you simply can't do it with today's technology on a leading-edge node.

However ATI proves it is feasible to put 2.4B xtors onto a monolithic IC given the xtor density they arrived at for their 40nm-based chips, not that doing it would necessarily be desirable or to the maximum benefit of all other designer/layout metrics of success, merely that it is feasible (the word I intentionally elected to employ in my post) based on known physical constraints and boundary conditions of the underlying manufacturing technology.

I was merely pointing out that it was not entirely out of the question as was originally implied in the post I quoted.

A comment regarding xtor density...many folks (I have gathered) are unawares that xtors have varying width and length even within the same process technology. Depending on what the circuits themselves are doing (in terms of raw TTL) the length and width of the xtors will vary from circuit to circuit on the chip. Some will be really tiny xtors, as tiny as the process technology allows (this is usually your sram xtors), and others will be huge micron-sized gargantuan xtors designed to really push the amps when turned on and be a solid resistor when turned off (I/O xtors, etc).

Using xtor count and density metrics for comparing architectures is a kinda flimsy analysis if there aren't some other boundary conditions taken into account, like solely using GHz to compare GPU's or solely using power consumption to make comparisons. Xtor density can be useful in making some loose comparison and helps assist in communicating ideas and concepts effectively in forums and the like, but its not a hard/fast metric of success so don't get too hung up on it.

I understand your point better now IDC, thanks for the explanation.

It's true that the transistor density on the same chip varies according to their use etc, if we take the K10 architecture as an example, even the L2 and L3 cache density is different.

The GT300 is probably going to be very complex, because NV wants to increase GPU compute performance (do more CPU work on the GPU), while increasing 3D performance over the last generation at the same time, so the chip will have many different parts for different functions. ATI is more concerned with 3D performance and keeping the die size small.

So as you say it's possible for a GT300 with 2.4B transistors to get ~ 400 mm^2 die size, I don't see it happening. Unless the MIMD design changes things?

 

[Creig]

Originally posted by: Keysplayr

Originally posted by: thilan29

Originally posted by: Creig

Originally posted by: thilan29
Some more info (2.4billion transistors apparently):
http://www.hardware-infos.com/...hp?news=2944&sprache=1

There's no way they're going to get 2.4 billion transistors working on a single die at 40nm. If they ever tried, their yields would be somewhere around 2%.

What makes you so sure?

He isn't.

Thank you for pointing out the obvious, Keys. But since he wasn't asking you a question, perhaps you'd allow me to answer for myself from now on? Hmmmmm?


thinlan29, I was using 2% simply to show that attempting to get 2.4 billion transistors working properly on an already troubled 40nm process would, in my opinion, generate unacceptably low yields.

The GT200, at 1.4 billion transistors, had a yield rumored to be around 40% at launch. And that was on an already proven 65nm process. So the GT300 now has both the complexity of its own 2.4 billion transistor design plus the already low yields coming out of 40nm working against it. Look at the 4770. It's only an 826 million transitor part on 40nm and TSMC had difficulty producing as many as ATI wanted due to yield issues. Add in the increased leakage issues that seem to be inherent to 40nm in general and, at least to me, it seems that it will extremely difficult for Nvidia to get good yields.

Will the 40nm process yield increase by the time the GT300 is ready for production? Of course. But by how much will it mature? That's the question. It will be interesting to learn how many of those 2.4 billion transistors are dedicated simply to redundancy in an attempt to increase yields.

Do I know any this for sure? Of course not, nobody here does. It's simply my conjecture. But those issues are definitely something that Nvidia will have to deal with, and they're biggies.

 

[Keysplayr]

You're absolutely welcome! But you might of explained why you thought that right in the post that you declared it. And maybe it wouldn't have left Thilan wondering what made you sure of it. Because you "sounded" damn sure.

40nm is troubled, now. It may or may not be, by then. "then" being the time production would hopefully ramp up for both AMD and ATI on 40nm. You guys do jump the gun a lot. But we'll see. Like anything else.

 

[Keysplayr]

Originally posted by: MarcVenice

Originally posted by: dreddfunk
Guys, I think this is all a mountain over a mole-hill. I simply think what Marc is trying to say is that he feels:

1) G80 wasn't initially designed with GPGPU in mind.
2) That, despite the close proximity of CUDA's launch to G80, the development cycle for G80 was long enough for it to plausibly be an after-the-fact (of design) decision on NV's part
3) That the architecture of any GPU has the potential for making a good GPGPU, if the company throws enough weight behind developing the API, etc., for such applications.
4) That NV decided to throw enough weight behind their GPU's GPGPU potential to create CUDA, and make a stronger move than AMD to go after the GPGPU market (which seems like a good marketig move now, so he's complimenting NV here).

I just don't see this as a slight to NV at all--nor does it make ATI look like a savant. He's not saying that CUDA is an 'accident' or 'lucky'. I think he's merely trying to point out that NV may not have had to do very much (if anything) on a hardware side to make G80/GT200 good GPGPUs.

I can't evaluate that statement (or Marc's position), as I'm no engineer. If someone is a credible GPU engineer here, then perhaps they could explain to us just what hardware differences are required, or if it is merely building the proper software to access the hardware. I admit to being confused. Some seem to be saying that NV had to consider GPGPU a lot when designing the G80/GT200, and that it impacted the number of transistors and die size in some way, but we're short of verifiable information--or even truly knowledgeable speculation.

Honestly, however, I think people are looking for things to interpret as slights in Marc's comments.

IDC - it's really not like your comparisons of memory or CPUs. What he's saying is more like this: if we design a truck to haul lumber, which has a large, flat bed, behind the cab, it would be no surprise that it would also be good at hauling bricks. After all, it's good at hauling things that can fit into large, flat beds.

Thank you for clarifying

Hey Marc. I did some digging for you when it comes to your theory.

Here is what I know:

G80 launched November 8 2006.
G80 Launch

CUDA launched on the same day. November 8 2006 with SDK ready to download and go.
CUDA Launch

Nvidia had been planning for about 2+ years prior to the launch of the GeForce 8 series that they wanted to make their GPUs more general purpose and to give them the ability to run real computing languages like C, and now OpenCL and DirectX Compute.

Marc, your quote: "But I doubt they had CUDA in mind when designing G80, which they started in 2004 maybe?"

Answer: You don?t drop a computing architecture into a GPU at the last minute. They even recruited real computing engineers like John Nickolls, who is the daddy of the CUDA architecture. He was at MasPar where he had spent much of his career developing highly parallel computers.

Marc, another quote: "Also, CUDA is based on C, as far as my understanding goes of programming, that's just a programming language, that Nvidia somehow got to work on their gpu's. It can't be compared to the x86 or sse-extensions."

Answer: NVIDIA ?somehow got it to work? by integrating specific hardware that is able to understand C in addition to graphics."

Now are you understanding the large transistor count? About 20% of the transistor budget was utilized for compute functions, which cannot be used for graphics.

Marc. Nvidia planned this from the very beginning. At LEAST two years prior to the launch of G80.

I just thought you'd want to know this. You were so convinced otherwise.

 

[AzN]

Originally posted by: Creig

Originally posted by: Keysplayr

He isn't.

Do I know any this for sure? Of course not, nobody here does.

Seems Keys answered his question correctly.

 

[cbn]

So how much VRAM do we think GT300 will get? 1.5 GB or 2.0 GB?

 

[Keysplayr]

Originally posted by: Just learning
So how much VRAM do we think GT300 will get? 1.5 GB or 2.0 GB?

1GB or 2GB. I don't think the 512 bit bus would allow for a 1.5GB setup. If it is in fact 512 bit. Somebody do the math, I'm too tired. LOL.

 

[OCGuy]

Originally posted by: Just learning
So how much VRAM do we think GT300 will get? 1.5 GB or 2.0 GB?

Until you can show where > 1GB of RAM actually makes sense on mainstream monitor resolutions, I dont think they will want to build 2GB into the MSRP of the reference cards.

 

[cbn]

Originally posted by: OCguy

Originally posted by: Just learning
So how much VRAM do we think GT300 will get? 1.5 GB or 2.0 GB?

Until you can show where > 1GB of RAM actually makes sense on mainstream monitor resolutions, I dont think they will want to build 2GB into the MSRP of the reference cards.

I once saw someone here post that Crysis uses up to 1.4 GB of VRAM....but that is just one game.

Personally I like the idea of Games that use long View Distances but these don't seem to be implemented at the moment (for obvious reasons). Don't long view distances require more VRAM?

 

[Keysplayr]

It probably can at it's UBER highest settings and resolution. I know it uses about 800MB at high settings at 1680x1050 no AA. That's pretty high memory usage. But nice and playable on cards with 640MB of memory and up with smoothness. Any 512 card I have noticed stuttering at these settings. 8800GTS640 actually played the game smoother than a 8800GTS512. Lower framerates, but next to no stuttering with the 640. Just FYI.

 

[Rusin]

http://www.hardware-infos.com/...hp?news=2952&sprache=1
So GT300 has already taped out

 

[Blazer7]

These are definitely good news but that's only a phase. The next one is debuging and as this is a monster of a chip it will take quite some time to debug.

What are the chances that they won't run into anything serious that will make them go for a re-spin?

 

[ilkhan]

If its only one re-spin then Oct is do-able. If they need more it'd have to get pushed out to later.

 

[Idontcare]

Originally posted by: ilkhan
If its only one re-spin then Oct is do-able. If they need more it'd have to get pushed out to later.

Still boggles my mind when I contemplate the possibility of having 2.4B xtors wired together on one monolithic IC.

Further boggles my mind to consider that thanks to the parallel advances made in debug/verification the engineers can iterate thru this phase (and repeat when necessary) in a matter of months...all for a commodity consumer IC that won't be sold for more than $1k at the absolute tops.

The scale of it all is just astounding. To see it be treated as almost pedestrian (which it is) really drives home how advanced so many aspects of IC design and fabrication has become.

 

[Rusin]

Originally posted by: ilkhan
If its only one re-spin then Oct is do-able. If they need more it'd have to get pushed out to later.

G80 taped out in July and G80 was released in November after serious amount of trouble..

 

[Keysplayr]

Originally posted by: Acanthus
That chip will be large, even at 40nm.

MIMD processing cores are a lot larger than SIMD.

This spec sheet looks like a dual chip solution to me.

Transistor density would help with the die size.

 

[SickBeast]

Originally posted by: Keysplayr

Originally posted by: Acanthus
That chip will be large, even at 40nm.

MIMD processing cores are a lot larger than SIMD.

This spec sheet looks like a dual chip solution to me.

Transistor density would help with the die size.

Given the fact that TSMC is having trouble producing simple chips like the 4770 at 40nm, I can see why people are worried about monolithic chips like the GT300.

 

[Idontcare]

Originally posted by: SickBeast

Originally posted by: Keysplayr

Originally posted by: Acanthus
That chip will be large, even at 40nm.

MIMD processing cores are a lot larger than SIMD.

This spec sheet looks like a dual chip solution to me.

Transistor density would help with the die size.

Given the fact that TSMC is having trouble producing simple chips like the 4770 at 40nm, I can see why people are worried about monolithic chips like the GT300.

From a fab's perspective its a long time between now and Oct. A very long time.

 

[SickBeast]

Originally posted by: Idontcare

Originally posted by: SickBeast

Originally posted by: Keysplayr

Originally posted by: Acanthus
That chip will be large, even at 40nm.

MIMD processing cores are a lot larger than SIMD.

This spec sheet looks like a dual chip solution to me.

Transistor density would help with the die size.

Given the fact that TSMC is having trouble producing simple chips like the 4770 at 40nm, I can see why people are worried about monolithic chips like the GT300.

From a fab's perspective its a long time between now and Oct. A very long time.

Apparently they're trying to tape out the GT300 right now.

 

[Wreckage]

Originally posted by: SickBeast

Apparently they're trying to tape out the GT300 right now.

Apparently you did not even read this page

Originally posted by: Rusin
http://www.hardware-infos.com/...hp?news=2952&sprache=1
So GT300 has already taped out

 

[SickBeast]

Originally posted by: Wreckage

Originally posted by: SickBeast

Apparently they're trying to tape out the GT300 right now.

Apparently you did not even read this page

Originally posted by: Rusin
http://www.hardware-infos.com/...hp?news=2952&sprache=1
So GT300 has already taped out

Yeah and they could not confirm that NV has successfully completed taping out the chip. It still needs to be fully de-bugged. It sounds like they just completed the first spin which means they are still a ways off. It's still impressive, don't get me wrong.