Quite honestly, I can't grasp why everyone is trying to develop a wire-based transmission protocol of their own nowadays.
We have sata, usb, displayport, hdmi, thunderbolt and a plump batch of other standards all pretty much offering the same thing in terms of bandwidth and all of them pretty much evolving in parallel as in each next gen of one matching the next gen of the others.
So why aren't cable-based standards starting to converge into fewer, god forbid one and only standard?
For example (and I'm not an USB advocate):
USB 3.1 spec provides up to 100W of power and up to 10 Gbit/s data rate (both maximums not available at the same time).
This bandwidth matches all other bandwidths when doubled (DP currently has 17 Gbits/s).
As in PCIex, the USB connector could easily have been designed as 1, 2, 4, 8 and 16 lane (feel free to leave any intermediate steps out or add a new, wider one), which would cover one helluva bandwidth spectrum (16x10Gbit/s == mega drool).
Such a design would easily cover current bandwidth requirements and massively decrease costs because only one type of interface chips would have to be made, not to mention that SOCs would be safe to implement this on-die. This would make it sooooooo easy to support any number of extensions / peripherals just by adding a few ports to the SOC. And if one needed more, they would just add an usb hub and happily whistle away.
So why aren't they? (whistling away, that is)
We have sata, usb, displayport, hdmi, thunderbolt and a plump batch of other standards all pretty much offering the same thing in terms of bandwidth and all of them pretty much evolving in parallel as in each next gen of one matching the next gen of the others.
So why aren't cable-based standards starting to converge into fewer, god forbid one and only standard?
For example (and I'm not an USB advocate):
USB 3.1 spec provides up to 100W of power and up to 10 Gbit/s data rate (both maximums not available at the same time).
This bandwidth matches all other bandwidths when doubled (DP currently has 17 Gbits/s).
As in PCIex, the USB connector could easily have been designed as 1, 2, 4, 8 and 16 lane (feel free to leave any intermediate steps out or add a new, wider one), which would cover one helluva bandwidth spectrum (16x10Gbit/s == mega drool).
Such a design would easily cover current bandwidth requirements and massively decrease costs because only one type of interface chips would have to be made, not to mention that SOCs would be safe to implement this on-die. This would make it sooooooo easy to support any number of extensions / peripherals just by adding a few ports to the SOC. And if one needed more, they would just add an usb hub and happily whistle away.
So why aren't they? (whistling away, that is)