Ding ding ding ding!
Says who? Do you really think that you have an idea that no other CPU architect has ever had, that will unlock mountains of performance? And where do you get your numbers from? 40x? You say it is not a fantasy, except that it is. What "prototype" do you have? Who fabbed it?
EDIT
Why would they want the competition? Not that there would be any...
Simple. 40x comes from the extreme density of the various native x86 instructions
Intel and AMD RISC dynarecs are
power hungry and
inefficient compared to this, with way
lower IPC. As to why 'nobody else has ever thought of this before':
that's not true. Many people have thought of elements of this design. They're in the mid-2000s AMD GPUs, the Elbrus 2000, the
failed Intel Itanium (Intel,
the #1 chipmaker,
failed at this because of their arrogance around compilers), and even arguably some of the SPARCs and IBM POWERs.
But I've added some 'secret' sauce. With the number of transistors you can fit on a chip these days, you can have a pure CISC, VLIW CPU...
That is also pipelined
That has many parallel pipelines to handle the complexity of pure CISC code
That can also execute said pipelined instructions out-of-order (speculative execution)
That has a large HBM2 cache to absorb the branch misprediction issues.
That can
make enormous amounts of money in a brutal bidding war for the server x86 market in late 2019-mid 2020.
Boom headshot?
The above underlined comment
is not needed, and did not add anything
positive to this debate. Save that for the
social sub-forums.
AT Mod Usandthem