Optical CORDIC and VLIW for next-gen x86?

[Headfoot]

If you want to see how modern consumer facing VLIW would work, look no further than nVidia Denver. Probably the most modern and interesting take on it. And ultimately seeing limited success - it is able to stick with the herd for the most part but has now been outpaced.

If you need parallel execution, better to go straight to GPU or the increasingly easy to program FPGAs, or Xeon Phi. VLIW seems a dead dream now.

 

[Headfoot]

It is not enough to design a single ISA and chip. You must upkeep that chip, support it, promise many compatible iterations. No one is going to buy into a single chip for general purpose CPU only to know they will have to switch back to Intel or AMD. Credibility, longevity of the enterprise, etc. are much bigger concerns even than the technology.

Highly focused chips experience this too but to a lesser degree - if you can do your one specialty very well then it might be worth using it even if I have to switch vendors next generation. Things like DSPs, etc.

 

[eton975]

The design is being prototyped as we speak.

300mm high volume production will most likely exist by Q1 2021.


Can't remember where/when I thought this was actually happening... no solid evidence.

I apologise, it's been an exhausting 4 months.
(Edited)

 

[SarahKerrigan]

I know this is going to sound like I'm being sarcastic and I really promise I'm not, but has there ever been a VLIW design that was a sustained success in any field? The best case I can come up with was Terascale 1/2/3 and even then those cards only hung around for 3~4 years before being phased out for GCN, which proved better in basically every way (in part due to the 28 nm admittedly). Itanium might have been around longer, but it would be hard to classify as much of a success story either.

SHARC, C6000, Hexagon, various Xtensa and Ceva cores, arguably Midgard/Bifrost (they aren't conventional VLIW as their ops run sequentially rather than in parallel, but are multiple ops in one instruction word.)

 

[eton975]

.......................................



No selling outside of the FS/T forum.

Also no selling of items not in your possession.


esquared
Anandtech Forum Director

 

[Thunder 57]

The design is being prototyped as we speak.

300mm high volume production will most likely exist by Q1 2021.

I'm sure it is. On napkins, perhaps?

Why do you think no one is taking you seriously? Because there is no chance of this going anywhere. In the spirit of March Madness, you'd have a better chance of picking a perfect bracket than what you propose.

That's before you get to IP. AMD or Via will license you x86, why? Out of the goodness of their hearts? Then you list some fantasy CPUID where half the extensions are Intel's, so you would have to deal with them anyway.

 

[eton975]

I'm sure it is. On napkins, perhaps?

Why do you think no one is taking you seriously? Because there is no chance of this going anywhere. In the spirit of March Madness, you'd have a better chance of picking a perfect bracket than what you propose.

That's before you get to IP. AMD or Via will license you x86, why? Out of the goodness of their hearts? Then you list some fantasy CPUID where half the extensions are Intel's, so you would have to deal with them anyway.

Because they would be given the opportunity to make a lot of money from this design by working together. If they don't, we flat-out refuse to share any SystemVerilog and process node IP with them, and pit them against each other until one cracks and agrees to do the 1486, while the other misses out on the money and maybe even goes bankrupt.

This is not a fantasy story bud. Pure CISC, OoO, pipelined and dynarecced-into-macroops x86 can be 40x or more faster, with the validation being extremely difficult and a large die size....

But who better to go for for simulation and validation than an established player like VIA or AMD, if not a datacentre or BOINC? And the large die size is not a problem if we can sell each CPU for $500K or more apiece in 2019 200mm wafer production, while splitting it into many smaller if less dense die for high volume/high yield production.

Thoughts?

 

[CHADBOGA]

Thoughts?

You are wasting everyone's time.

 

[Thunder 57]

You are wasting everyone's time.

Ding ding ding ding!

This is not a fantasy story bud. Pure CISC, OoO, pipelined and dynarecced-into-macroops x86 can be 40x or more faster, with the validation being extremely difficult and a large die size.

Says who? Do you really think that you have an idea that no other CPU architect has ever had, that will unlock mountains of performance? And where do you get your numbers from? 40x? You say it is not a fantasy, except that it is. What "prototype" do you have? Who fabbed it?

EDIT

But who better to go for for simulation and validation than an established player like VIA or AMD

Why would they want the competition? Not that there would be any...

 

[eton975]

Ding ding ding ding!



Says who? Do you really think that you have an idea that no other CPU architect has ever had, that will unlock mountains of performance? And where do you get your numbers from? 40x? You say it is not a fantasy, except that it is. What "prototype" do you have? Who fabbed it?

EDIT



Why would they want the competition? Not that there would be any...

Simple. 40x comes from the extreme density of the various native x86 instructions

Intel and AMD RISC dynarecs are power hungry and inefficient compared to this, with way lower IPC. As to why 'nobody else has ever thought of this before': that's not true. Many people have thought of elements of this design. They're in the mid-2000s AMD GPUs, the Elbrus 2000, the failed Intel Itanium (Intel, the #1 chipmaker, failed at this because of their arrogance around compilers), and even arguably some of the SPARCs and IBM POWERs.

But I've added some 'secret' sauce. With the number of transistors you can fit on a chip these days, you can have a pure CISC, VLIW CPU...

That is also pipelined
That has many parallel pipelines to handle the complexity of pure CISC code
That can also execute said pipelined instructions out-of-order (speculative execution)
That has a large HBM2 cache to absorb the branch misprediction issues.
That can make enormous amounts of money in a brutal bidding war for the server x86 market in late 2019-mid 2020.

Boom headshot?

The above underlined comment
is not needed, and did not add anything
positive to this debate. Save that for the
social sub-forums.

AT Mod Usandthem

 

[eton975]

SHARC, C6000, Hexagon, various Xtensa and Ceva cores, arguably Midgard/Bifrost (they aren't conventional VLIW as their ops run sequentially rather than in parallel, but are multiple ops in one instruction word.)

This would be very much like Midgard. Sequentially executed, but pipelined and speculatively executed to increase serial performance, using a heuristic engine or just plain 'try every possibility!!!' for the simple predictable code. The differences are: it's x86, there's no RISC decode because it's inefficient and unnecessary with the massive amount of L3 (8MB) and HBM2 (4-8GB) available or stacked on top of the main CPU die. There is however, macro-op encode, where the CISC x86 instructions are ganged into 512-bit wide macroops and maybe even compressed with a hardware compressor (to squeeze EVEN MORE instructions in) for SIMD and/or AVX tasks with high ILP. This means 8-40x faster performance on unoptimised x87 or non-SSE/non-AVX code, because the CPU is literally optimising said instructions to run like said AVX ones in hardware, rather than blindly following the old inefficient code in order and thus slowly.

 

[Thunder 57]

Boom headshot?

You got some growing up to do. And you still haven't said where 40x comes from, other than you just picked a large number.

This is not OT or P&N.
We do not allow pics or
gifs for insults....or personal
insults or attacks, period.

AT Mod Usandthem