PCI lantency

[CTho9305]

There's a setting somewhere in the BIOS setup called PCI latency something. The default is 32. Does anyone know what it is? I've heard its the number of cycles a device gets before the bus switches to another device. Is that right? If so, why only 32 cycles - isn't that a really short time?

 

[SCSIRAID]

Its the minimum number of clocks that a device gets before it must give up the bus.

 

[CTho9305]

so a device uses at least 32 cycles before yielding the bus, but can use more? why set it at 32 then, instead of a really low number?

 

[SCSIRAID]

Yes it can use more. The master is awarded the bus via the GRANT signal. Once it is granted it can go like heck. If the PCI bus arbiter (traffic cop) gets requests from other masters wanting the bus it will turn GRANT off to the current owner.

EDIT to correct error....

That master must terminate if his counter has already decremented to zero. If not he can continue until it does. This guarantees a master a minimum time slice of bus time.

 

[Kitros]

I've just been confused.

CTho asked if a lower number would be better, thus minimizing latency?

Is this correct?

 

[SCSIRAID]

As with a lot of performance "knobs" you can turn... it depends... I know you didnt want to hear that. The impact of this value is multifold. It sets two things 1)How many clocks of guaranteed bustime does the granted master get and 2)How long does another master have to wait until the granted master must get off. If you crank the number up.. the guy currently on the bus gets to go longer and get more efficient usage from the bus BUT at the expense of the other guy.... If you crank the number down then the guy on the bus may just get started and get punched off but the guy causing him to get punched off doesnt have to wait long to get on (and then get punched off by the other guy). The least desirable of these is the second. Making the timer too small can reduce the system thruput since all the masters spend all their time arbitrating and getting just a little data thru.

Bottome line... I would leave it at 32. A lot of very smart guys came up with that as the default. If you are gonna mess with it I wouldnt make it smaller... I would make it bigger.

 

[nam ng]

<< I've just been confused.
CTho asked if a lower number would be better, thus minimizing latency?
Is this correct? >>


YES and NO.
Lower number minimize latency response but lower data throughput, poor performance.
Higher number maximize data throughput but worst latency response, lock-ups not response properly within time demand.

When optimizing the numbers, increase or decrease by factor of 16, this is the minimum clock cycles for servicing 16 IRQs.

 

[CTho9305]

I won't mess with it then. thanks