Really, my understanding was that the Cherry Trail silicon was actually exactly the same silicon as Braswell, just better binned, fused differently, and with things (like SATA) not bonded out to the package.
So, you could just sell the better binned, differently fused Apollo Lakes as Apollo Lakes.
There might be a legitimate difference. Pineview had quite a bit of difference from Medfield/Clover Trail.
It wasn't just TDPs. The mass Tablet market is likely closer to phones than PCs. That's served by Willow Trail/Morganfield. Then there's the PC-focused segment with higher platform power and PC level I/O's like SATA.
Here we see there was one document that listed Willow View (the only place I can find it) as the Willow Trail SoC, actually renamed to "Willow Trail SoC." Then on another roadmap it actually lists Morganfield as the Willow Trail SoC. Even more daunting is that the two documents have dates that are just a few days apart, but they're both pretty old (2013)
"Trail" is traditionally the platform, "-view" the SoC. Oakview/Oak Trail, Pineview/Pine Trail, Cloverview/Clover Trail.
Now the successor platform for Cherry Trail is Broxton and Broxton Pro, not Willow Trail.
As I understand, Broxton is like Silvermont and Airmont. Core names. Then you have the SoC-specific names, like "-view". Then you have platform specific names like "Trail".
So based on what Intel was saying we may be able to conclude as follows.
Platform:
Cherry Trail-->Willow Trail
Braswell-->Apollo Lake
Mooresfield-->Morganfield?
Core:
Silvermont/Airmont-->Broxton
Of course, with Broxton generation, Intel was supposed to unify Smartphones/Tablets. Unlike now where Cherry Trail uses Gen 8 Intel GPU + others while Mooresfield uses PowerVR + other differences.
And when Core enters on Phi, Atom will be history.
Unlikely. Until current "Core" chips become the "small" core. I think Core cores are 5x + the size. Broadwell is nearly 7mm, and Skylake is probably at 8-9mm2. Knights Landing's core with 512-bit vector execution units are only at 3mm2. And in achieving mass parallelism, the additions that Core has does nothing.