Originally posted by: Acanthus
Originally posted by: bryanW1995
why would the safe voltage ceiling be so low?Originally posted by: Acanthus
Originally posted by: HopJokey
One thing people are overlooking is that in the preview, Anand was able to push the A0 chip to 3.22Ghz on 1.15v!
Dont forget, however, that they wont tolerate "conroe like" voltages either.
The ceiling for safe voltage will be around 1.3v
Because the smaller you make the gates, the easier it is to slow roast them with voltage
They also require less voltage to run, so its a non issue as long as you know not to set it too high.
And the "safe" voltage bias you can place across adjacent copper lines scales linearly with node shrinkage so as to maintain same electric-field on the dielectric from node to node and maintain 10-year lifetime expecation for time-dependent dielectric breakdown (tddb) strength.
Expect minimum metal half-pitch at 65nm node to be 90nm and the minimum half-pitch at 45nm node to be 70nm and you can quickly determine that you must scale the voltage by approximately 70nm/90nm = 0.778x or else you can expect a reduced tddb (reduced chip lifetime from e-field induced failure mechanisms).