Power-Consumption Scaling with Clockspeed and Vcc for the i7-2600K

[Idontcare]

Can you please re-run the results at different temperatures to add another dimension to power scaling?

I kid, that must have been an insane amount of work. I am curious to your findings that system power consumption stays the same despite clock speed. I thought working the RAM that much harder would have increased it at least a few watts.

The ram consumes fixed power more or less because the power draw on dimms comes from the refresh cycle that has to refresh all the cells every few microseconds regardless whether the computer is accessing them or not.

Accessing the dimms is merely a drop in the bucket of added power there.

That said, the one thing that varied during the tests was the fan speed on the H100. I expected this to result in a measurable variation in the system level power usage and yet apparently, to whatever extent the system power did fluctuate and vary over the tests it was below the detection limits of the kill-a-watt.

 

[Idontcare]

Is there a tl;dr version? All I get is the curve starts going up at a steeper angle around 4.5GHz.

Post 5 I suppose would be the tl;dr version.

But yes, 4.5GHz is definitely the edge of the "sweet spot" that starts around 4GHz.

To go from 4.5GHz to 5GHz (an ~11% increase) requires a near 50% increase in CPU power consumption D:

 

[PreferLinux]

Seems that this arise from complementary push pulls increasing
crossconduction with frequency increasing, such that a frequency
high enough , close to the devices frequency transition, the two
legs of the push pulls are simultaneously conducting , with the current
limited only by the devices finite transconductance , wich as such ,
will yield about a quintic law out from a law that is basicaly exponential
if it was not restrained by the said gm (transconductance) finite value..

On another note , a very good article , indeed...

Sure you don't mean quadratic? Exponential is y=a^x or y=ae^x

 

[Idontcare]

Seems that this arise from complementary push pulls increasing
crossconduction with frequency increasing, such that a frequency
high enough , close to the devices frequency transition, the two
legs of the push pulls are simultaneously conducting , with the current
limited only by the devices finite transconductance , wich as such ,
will yield about a quintic law out from a law that is basicaly exponential
if it was not restrained by the said gm (transconductance) finite value..

On another note , a very good article , indeed...

I'm so glad you chimed in on this Abwx, I'm actually at quite a loss, personally, to explain the specific device physics that are the cause of this result. (elaborate way to say "I don't have a d'ing clue why this is the case ")

The commonly cited device physics responsible for transition power are, naturally, the invocation of DC charging of a capacitor model and the energy stored and released per "charge/discharge cycle".

Just picking one out of a few thousand available references to this model in google, this one by Agrawal and Srivaths seems nice and succinct.

Using the capacitor charging/discharging model as the basis for the energy consumed in a single transistor switch event is what begets the "1/2 * C * V^2" model for the device physics that explains the transition power.

But we don't see a quadratic. It is clearly a near-quintic. So what physics are we to invoke such that the model of the device physics is better represented?

I am at a loss to explain (mathematically and with a physical model to speak to) why the exponent would ever become greater than 2. Any electrical engineers in the audience that can expand on this?

 

[CTho9305]

Great post, IDC. A few comments:

Static power is probably exponential (x^Vcc), not linear or polynomial (Vcc^x). It's really bothering me that a linear equation fit your data so well, and I'm having a hard time coming up with a justification for that.

Pshort-circuit has to be dependent on voltage, if only because there is none when you operate close to the transistor threshold voltage (or maybe even has high as 2*Vt?). I don't know the actual relationship offhand, but my suspicion is that it has to be quadratic (possibly a form like (Vcc-something)^2). Additional complexity comes from the fact that you get faster transitions at higher voltages (so, there's more current, but for less time). The fact that you're not getting a y-intercept of 0 for all three curves on the "voltage-vs-power at 3 frequencies" chart concerns me.

Switching power really should be quadratic...I suspect the other things I pointed out are why you arrived at a 5th-power scaling for this component.

How consistent was temperature across your vmin-fmin -> vmax-fmax range? In industry it takes pretty fancy cooling to keep Tj consistent across a wide range of loads like that.

I'm wondering if something else in the system (e.g. the voltage regulator) is behaving in a way that hides parts of the data (e.g. by becoming more inefficient at lower voltages).

Maybe IR drop in the package or chip power grid (V = IR, so at big I, you get some V across the power grid) is throwing some complexity into the data... under load, the voltage seen at the transistors will be somewhat lower than the voltage applied at the pins. The equation for power is actually V * deltaV; for CMOS that's normally V*V (because you get full-rail swing), but if you're dropping 100mV in the grid at high voltage & load, your power consumption is V*(V-100mV) while at low voltage it'll be V*(V-a smaller number).

In post #6 you have a plot that looks a lot like a shmoo - did you include the points at Vmin in your data when fitting curves? If so, I'd suggest removing them... just note that the curves only apply for Vcc > Vmin and the chip doesn't work at any frequency once you go below that voltage.

 

[Idontcare]

Static power is probably exponential (x^Vcc), not linear or polynomial (Vcc^x). It's really bothering me that a linear equation fit your data so well, and I'm having a hard time coming up with a justification for that.

Pshort-circuit has to be dependent on voltage, if only because there is none when you operate close to the transistor threshold voltage (or maybe even has high as 2*Vt?). I don't know the actual relationship offhand, but my suspicion is that it has to be quadratic (possibly a form like (Vcc-something)^2). Additional complexity comes from the fact that you get faster transitions at higher voltages (so, there's more current, but for less time). The fact that you're not getting a y-intercept of 0 for all three curves on the "voltage-vs-power at 3 frequencies" chart concerns me.

Could you take a look at the slides 12-23 of the following:
http://www.eng.auburn.edu/~agrawvd/COURSE/SUM_07_HYD/lp_hyd_2.ppt

Are they making assumptions that are just wrong when they come to state the equation shown on page 18?

Also, I would say don't conflate the existence of non-zero intercepts being used for deconvoluting the parameter's contributions to the model as being somehow real or implied to be real. It is an artificial construct intentionally created so as to partition the underlying contributors in a way that makes it easy to "project them out from the data".

Decompositional analysis is not saying the y-intercept is non-zero, the decompositional analysis is just a tool for extracting the parameters necessary to support the voltage and clockspeed versus power-consumption variation for the actual data points collected.

I'm probably not saying that quite right, or with a vernacular that is not generalized enough to span the chasm of our respective backgrounds.

Switching power really should be quadratic...I suspect the other things I pointed out are why you arrived at a 5th-power scaling for this component.

How consistent was temperature across your vmin-fmin -> vmax-fmax range? In industry it takes pretty fancy cooling to keep Tj consistent across a wide range of loads like that.

Not well controlled at all, by any means, that was part of my surprise as I lamented above about the cheap tools I used.

Temperatures ranged from ~35C to 90C across the tests.

What is intriguing is that the 2GHz vs. 3GHz vs. 4GHz tests were clearly done at different temperatures (2GHz vs 4GHz have markedly different temps at every voltage point) and yet they were all fit to the exact same exponent (~4.9).

All I can conclude from this is that to whatever extent the operating temperature matters (and without question it does matter) it matters to such a little extent that its impact here across these temperature ranges was so small that it did not result in a materially significant propagation of error.

In post #6 you have a plot that looks a lot like a shmoo - did you include the points at Vmin in your data when fitting curves? If so, I'd suggest removing them... just note that the curves only apply for Vcc > Vmin and the chip doesn't work at any frequency once you go below that voltage.

No, that was by design for the express purpose of "testing" the resultant equation at the top of post #5.

All the parameters here were from decompositional analysis of the data shown in the following graph:

None of the data in the following graph were used for the decompositional analysis: (ignore the black line)

Only once I had the equation's parameters as detailed above did I then compute the black line for the data, computed the least-squares Pearson R^2 value:

Again, the black line above and the R^2 value are not implied to be "curve fit". It is overlaid, purely overlaid. Data versus the model, and the data shown here (the blue data points) were not used in the computation of the parameters of the model.

I included the data in the graphs shown in post 6 just for sake of completion, to showcase the sum total dataset involved in this study. And also to detail a pseudo-shmoo plot (pseudo because temperatures are not rigorously held constant).

I do plan to do some temperature-variation studies as well, once I finalize some other ongoing projects that are chronicled in the case and cooling section.

 

[veri745]

This is amazing, and it must have taken an extraordinary amount of work to produce.

I would love to see any continuation on temperature variation. I know that increasing temperature can dramatically increase static power draw.

Do you have any data what what temperatures you were reading at say 2.5GHz vs 4.5 GHz? under max load in your experiment?

 

[Abwx]

I'm so glad you chimed in on this Abwx, I'm actually at quite a loss, personally, to explain the specific device physics that are the cause of this result. (elaborate way to say "I don't have a d'ing clue why this is the case ")

The commonly cited device physics responsible for transition power are, naturally, the invocation of DC charging of a capacitor model and the energy stored and released per "charge/discharge cycle".

Just picking one out of a few thousand available references to this model in google, this one by Agrawal and Srivaths seems nice and succinct.

Using the capacitor charging/discharging model as the basis for the energy consumed in a single transistor switch event is what begets the "1/2 * C * V^2" model for the device physics that explains the transition power.

But we don't see a quadratic. It is clearly a near-quintic. So what physics are we to invoke such that the model of the device physics is better represented?

I am at a loss to explain (mathematically and with a physical model to speak to) why the exponent would ever become greater than 2. Any electrical engineers in the audience that can expand on this?

The Cl capacitor energy absorbtion is linear with rising frequency,
but the phenomenon of crossconduction is far more energy
consuming with increasing frequency.

When the upper device try to stop conducting , it will take some
time for the conduction to actually stop.

If in the same time the lower device start conducting faster
than the upper quit conduction , the current will rise exponentialy
as a function of the time of simultaneous conduction , the whole
push pull will then simply be a short circuit whose current will
be limited by the devices intrinsical resistance.

The higher the frequency the higher the duration of crossconduction.

"Mosfet haut" and "Mosfet bas" means upper mosfet device
and lower mosfet device (of a push pull) respectively.

"Vseuil" means threshold voltage.

 

[Kenmitch]

IDC = Super Nerd

Looks like you had alot of fun doing this!

 

[ThatsABigOne]

Thank you for the analysis, Idontcare. You did great, extensive work! You are now a professional reviewer... according to my eyes. I loved your delidding gtx460 thread. I was tempted to do the same with GTX570, but I use stock cooling, which is very good.

 

[Hauk]

Wow IDC, this is incredible work! Ur pretty smart..

 

[aigomorla]

lulz...

now u guys... calculate how many amps are being fed via cpu socket to that cpu.

So assume using idc's numbers the cpu is pulling roughly 200W or power... and ur running it at 1.375vcore.

200W / 1.375V ~ 145 AMPS being fed though less then 1155 pins to the CPU.

^ now u guys see why i always push people to get BEEFY boards if they really want to overclock... its not just what options the board has... but also down to how well it was made.

IDC = Super Nerd

Looks like you had alot of fun doing this!

No wait til u see ruby come in and challange him.
Then u swear there speaking english.. but... it sounds chinese... <--- dont mean any offense to this...

 

[Idontcare]

This is amazing, and it must have taken an extraordinary amount of work to produce.

I would love to see any continuation on temperature variation. I know that increasing temperature can dramatically increase static power draw.

Do you have any data what what temperatures you were reading at say 2.5GHz vs 4.5 GHz? under max load in your experiment?

I logged temperature data for all data points.

At 1.491V and 1.6GHz the peak temperature was 57.2°C
At 1.491V and 3.0GHz the peak temperature was 72.7°C
At 1.491V and 5.0GHz the peak temperature was 93.1°C

At 0.972V and 1.6GHz the peak temperature was 37.2°C
At 0.972V and 3.0GHz the peak temperature was 44.2°C

(5Ghz was not possible at 0.972V)

I was thinking of pulling together two more pseudo-articles, one detailing the impact of temperature on the minimum voltage necessary to be IBT stable at a given clockspeed, the second being an overview of what we are actually attempting to accomplish when we "stress test" our cpu's for stability (beware of the Weibull! ).

The Cl capacitor energy absorbtion is linear with rising frequency,
but the phenomenon of crossconduction is far more energy
consuming with increasing frequency.

When the upper device try to stop conducting , it will take some
time for the conduction to actually stop.

If in the same time the lower device start conducting faster
than the upper quit conduction , the current will rise exponentialy
as a function of the time of simultaneous conduction , the whole
push pull will then simply be a short circuit whose current will
be limited by the devices intrinsical resistance.

The higher the frequency the higher the duration of crossconduction.

"Mosfet haut" and "Mosfet bas" means upper mosfet device
and lower mosfet device (of a push pull) respectively.

"Vseuil" means threshold voltage.

Awesome, that is great :thumbsup:

What I don't know about device physics could fill an internet. I really appreciate you taking the time to expand on this.

Would you expect this to be dependent on the architecture or the process tech? The ~4.9 exponent observed here, would you expect this to be more intrinsic to Intel's 32nm process tech itself? (and as such it would be observed, maybe not exactly the same number, in other 32nm Intel parts)

I'm now even more curious to see how GloFo's 32nm turns out in this sort of an analysis. Must get my hands on an unlocked Llano or FX bulldozer!

 

[CTho9305]

I hate when the forum software doesn't nest quotes

Could you take a look at the slides 12-23 of the following:
http://www.eng.auburn.edu/~agrawvd/COURSE/SUM_07_HYD/lp_hyd_2.ppt

Are they making assumptions that are just wrong when they come to state the equation shown on page 18?

Nope, but if you're only looking at page 18, they hid some Vdd's inside Esc - see slide 15. Note that there's also a Vdd hidden inside isc (short-circuit current) which doesn't appear to be on any of the slides but is obvious if you look at any MOSFET curves (look for a plot of Ids for a given Vgs). Also note that Esc is zero when Vdd <= Vtn + Vtp.

Also, I would say don't conflate the existence of non-zero intercepts being used for deconvoluting the parameter's contributions to the model as being somehow real or implied to be real. It is an artificial construct intentionally created so as to partition the underlying contributors in a way that makes it easy to "project them out from the data".

Decompositional analysis is not saying the y-intercept is non-zero, the decompositional analysis is just a tool for extracting the parameters necessary to support the voltage and clockspeed versus power-consumption variation for the actual data points collected.

I'm probably not saying that quite right, or with a vernacular that is not generalized enough to span the chasm of our respective backgrounds.

My concern is mostly that your really cool graph showing the components of CPU power is completely incorrect . I don't dispute that you broke the components into... something...but I don't think those somethings are what you think they are.

Not well controlled at all, by any means, that was part of my surprise as I lamented above about the cheap tools I used.

Temperatures ranged from ~35C to 90C across the tests.

Ok, then I absolutely have to dispute your finding of leakage / static power being linear. Leakage grows very rapidly with temperature, particularly at higher temperatures (it's exponential with respect to T).

What is intriguing is that the 2GHz vs. 3GHz vs. 4GHz tests were clearly done at different temperatures (2GHz vs 4GHz have markedly different temps at every voltage point) and yet they were all fit to the exact same exponent (~4.9).

All I can conclude from this is that to whatever extent the operating temperature matters (and without question it does matter) it matters to such a little extent that its impact here across these temperature ranges was so small that it did not result in a materially significant propagation of error.

Unless Intel's transistors break all the textbook & industry data I've seen, or their chips are almost purely dynamic-power-dominated*, that absolutely cannot be true. Do you have the ability to measure power at different temperatures but the same voltage & frequency (i.e. slow down fans?)

*We can deduce that static power is big enough to matter because they went to the trouble of implementing power gating

Do you get decent curve fits if you assume short circuit power is of the form:
(Vdd-something)^2 * something * frequency
and static current is of the form
something ^ (vdd * something)
? Maybe if you throw in some fudge factor for voltage regulator efficiency?

If you have a lot more time to throw at this, I'd be really interested in seeing a truer pseudo-shmoo, where you don't just do a vmin search at every frequency but also a vmax search (up to whatever point scares you). Given your finite cooling abilities, we might see some high-voltage roll-of where the curve ends curving back towards the right.

 

[Idontcare]

Do you get decent curve fits if you assume short circuit power is of the form:
(Vdd-something)^2 * something * frequency
and static current is of the form
something ^ (vdd * something)
? Maybe if you throw in some fudge factor for voltage regulator efficiency?

Sure:

121.0+6.94^(1.30*Vcc)+16.67*GHz*Vcc^2
R^2=0.995594860352

Surface plot is visually the same:

But at least now we aren't violating known laws of device physics!

I feel much better by this result, the world makes more sense once again.

I'm still a bit baffled how or why the lack of temperature control played so little effect in the observed results though. I really would have expected a stronger deviation between the model and the results.

 

[Idontcare]

If you have a lot more time to throw at this, I'd be really interested in seeing a truer pseudo-shmoo, where you don't just do a vmin search at every frequency but also a vmax search (up to whatever point scares you). Given your finite cooling abilities, we might see some high-voltage roll-of where the curve ends curving back towards the right.

The highest I was willing to put into the chip was the ~1.495V data series which extended the entire spectrum of clocks from 1.6GHz to 5GHz.

Wherever the "other side" of the shmoo plot resides, its above 1.5V.

 

[zlejedi]

Wow this got the electronic faculty student which sleeps deep inside me drooling

And You made it better than any professional reviewer I have seen so far.

PS. Is the 3D graph made using matlab ?

 

[Idontcare]

Thanks! Ordinarily I would have used mathematica to make my 3D graphs, but my Mathematica8 license was stuck in limbo waiting to be released so I could install it on my new computer which forced me to resort to looking for programs on the web that could do the job in a pinch.

That is when I found http://zunzun.com/ and realized just how awesome and simple it is. All the graphs were generated by the zunzun online program.

I'd be more than happy to share my dataset if people want to play around with it themselves. Not sure the best way to "upload" though. It's only 200 rows of data.

Let me see if I can embed it in a code field without buggering up the formating of the thread.

Training Set: (for model fitting)

Clockspeed (GHz) Vcc (V, measured) Power-Consumption @ Wall (W)
2.0 0.820 156
2.0 0.845 157
2.0 0.870 158
2.0 0.895 159
2.0 0.920 161
2.0 0.945 163
2.0 0.970 165
2.0 0.995 167
2.0 1.020 168
2.0 1.045 171
2.0 1.070 174
2.0 1.095 176
2.0 1.120 179
2.0 1.145 181
2.0 1.170 184
2.0 1.194 188
2.0 1.219 191
2.0 1.244 194
2.0 1.269 198
2.0 1.294 201
2.0 1.319 206
2.0 1.344 209
2.0 1.369 213
2.0 1.394 218
2.0 1.418 223
2.0 1.443 227
2.0 1.468 233
2.0 1.493 239
3.0 0.966 182
3.0 0.986 185
3.0 1.006 187
3.0 1.026 190
3.0 1.046 192
3.0 1.066 194
3.0 1.086 196
3.0 1.106 199
3.0 1.125 202
3.0 1.145 205
3.0 1.165 208
3.0 1.185 211
3.0 1.205 214
3.0 1.225 218
3.0 1.245 221
3.0 1.264 225
3.0 1.284 229
3.0 1.304 233
3.0 1.324 237
3.0 1.344 241
3.0 1.364 245
3.0 1.383 250
3.0 1.403 255
3.0 1.423 260
3.0 1.443 265
3.0 1.462 270
3.0 1.482 275
4.0 1.165 226
4.0 1.173 228
4.0 1.183 230
4.0 1.193 232
4.0 1.203 234
4.0 1.213 237
4.0 1.223 239
4.0 1.233 241
4.0 1.243 244
4.0 1.253 245
4.0 1.262 247
4.0 1.272 249
4.0 1.282 252
4.0 1.292 254
4.0 1.302 258
4.0 1.312 259
4.0 1.322 262
4.0 1.332 264
4.0 1.342 267
4.0 1.352 269
4.0 1.362 272
4.0 1.372 275
4.0 1.382 278
4.0 1.392 280
4.0 1.402 283
4.0 1.412 287
4.0 1.421 290
4.0 1.431 294
4.0 1.441 297
4.0 1.451 301
4.0 1.461 304
4.0 1.471 308
4.0 1.481 312
4.0 1.490 317
1.6 0.973 157
1.7 0.973 159
1.8 0.973 161
1.9 0.973 163
2.0 0.973 164
2.1 0.973 166
2.2 0.972 168
2.3 0.972 169
2.4 0.972 170
2.5 0.972 172
2.6 0.972 174
2.7 0.971 176
2.8 0.970 178
2.9 0.970 180
3.0 0.970 181
1.6 1.169 173
1.7 1.168 176
1.8 1.168 179
1.9 1.168 181
2.0 1.168 183
2.1 1.166 185
2.2 1.166 188
2.3 1.166 191
2.4 1.166 193
2.5 1.165 195
2.6 1.165 197
2.7 1.165 199
2.8 1.165 201
2.9 1.165 204
3.0 1.165 206
3.1 1.164 208
3.2 1.164 210
3.3 1.164 212
3.4 1.164 214
3.5 1.164 216
3.6 1.164 218
3.7 1.163 221
3.8 1.163 222
3.9 1.163 224
4.0 1.163 227
4.1 1.163 229
1.6 1.496 220
1.7 1.495 224
1.8 1.495 228
1.9 1.495 232
2.0 1.495 237
2.1 1.494 241
2.2 1.494 245
2.3 1.494 249
2.4 1.494 253
2.5 1.493 257
2.6 1.493 262
2.7 1.493 265
2.8 1.492 269
2.9 1.492 273
3.0 1.492 277
3.1 1.492 280
3.2 1.492 284
3.3 1.491 289
3.4 1.491 293
3.5 1.491 297
3.6 1.491 301
3.7 1.491 304
3.8 1.490 310
3.9 1.490 314
4.0 1.490 318
4.1 1.489 323
4.2 1.489 327
4.3 1.489 331
4.4 1.489 335
4.5 1.489 338
4.6 1.488 342
4.7 1.488 347
4.8 1.488 352
4.9 1.488 355
5.0 1.487 359

Test Set: Minimum voltage, clockspeed, and resultant power-consumption "test" dataset for testing model parameters

Clockspeed (GHz) Vcc (V, measured) Power-Consumption @ Wall (W)
1.6 0.803 149
1.7 0.802 151
1.8 0.802 151
1.9 0.807 153
2.0 0.822 155
2.1 0.837 157
2.2 0.851 159
2.3 0.866 162
2.4 0.881 165
2.5 0.896 168
2.6 0.915 170
2.7 0.925 173
2.8 0.940 176
2.9 0.956 178
3.0 0.969 182
3.1 0.984 184
3.2 0.994 189
3.3 1.018 192
3.4 1.038 195
3.5 1.058 201
3.6 1.073 206
3.7 1.093 210
3.8 1.118 216
3.9 1.138 221
4.0 1.162 226
4.1 1.188 232
4.2 1.209 240
4.3 1.236 249
4.4 1.267 258
4.5 1.290 268
4.6 1.330 282
4.7 1.369 296
4.8 1.405 312
4.9 1.444 334
5.0 1.488 354

 

[Mopetar]

So when are you going to start IdontcareTech?

Impressive work and an interesting read.

 

[Idontcare]

Nah, I'm happy right here where I am. The world at large has done nothing to deserve being penalized with exposure to my ignorance any more than is already inflicted on them

 

[kingey]

hi, im doing a report for a project and saw your oct 3, 2011 post on the i7-2600k, do you mind if i use your data for my report? thanks.