And the 16 core 5950x does more than the 32 core 7452 Rome, PPD wise.
Well, with such long tasks it will take a while until the PPD converge to some sort of average, but technically it may be plausible that the 5950X comes out ahead.
- Each PSP-LLR task works on approximately 20 MBytes of active data. (The bulk of its computing time is spent in a Fast Fourier Transform, and PSP-LLR's FFT data are that big.)
- The 5950X has got two last-level cache segments: 2× 32 MBytes large.
- The 7452 has got 8× 16 MBytes last-level cache segments.
So the 7452 has more cache in total than the 5950X, but unfortunately each of the cache segments of the 7452 is too small to hold an entire set of the LLR FFT data of one task. This means that the 7452 has to perform a lot more synchronization between CCXs, and a lot more memory accesses than the 5950X.
Now, 7452 has got 8 DDR4 RAM channels while the 5950X has got just 2 channels. (I assume you populated all of the channels in your EPYC computer.) This helps the 7452 but doesn't save it: Cache access is still a lot faster than RAM access.
Furthermore, 7452 has got a 155 W PPT limit, while 5950X has "only" 142 W PPT limit. (Both are the default values; 7452's can be increased to 180 W in the BIOS, and 5950X's can be increased to… I don't know, the moon?) But of these 155 W, the 7452 has to spend a good deal on inter-CCX communication and RAM I/O in case of PSP-LLR, whereas the 5950X can spend most of its 142 W on actual computation.
Granted, the 5950X has got only half of the core count than 7452. But a) 5950X's Zen 3 cores are a bit wider than 7452's Zen 2 cores, b) LLR uses a lot of FMA3 operations which are so power hungry, that the actual number of FMA execution units is a lot less important than the power (in Watts) which can be pumped through these units.
PS,
back in June when there was the ESP-LLR challenge, the tasks had only 15 MBytes FFT data. The Zen 2 cache arrangement was much better suited to those somewhat smaller tasks. But to reach top performance on Zen 2 with those 15 MBytes sized tasks, one had to coerce the operating system a little bit to really keep each task running on cores which are attached to the same cache segment; IOW prevent the OS from spreading one task across cache segments which would involve costly synchronization.
Edit:
I have a EPYC 7401P 24 cores, 2.4 ghz, and an EPYC 7551 32 core 2.4ghz, not sure the cache sizes.
Both have 8× 8 MBytes level-3 caches. But not just this is a handicap for them at PrimeGrid, but also the fact that Zen 1 cores have got only about half of the FMA execution bandwidth of Zen 2 cores.
AMD CPUs before Zen 2 and Intel CPUs before Haswell are not working well for PrimeGrid workloads.