Project with FPGA?

[Lord Banshee]

Ok i am taking a Digital Design this semester where we will learn how to built pretty much anything with VHDL.

I was thinking maybe when i am done the with the class (or know enough) that i could try to make a "simple" 3d vector pipeline. The FPGA and board i will be using is the following
http://www.bin-tek.com/item.aspx?cid=391&iid=btu001
And i was wondering if you think it is possible with this device and some nice circuit coding?

I have been doing some research on what exactly is needed for say a point in world space (x,y,z) to be view on a screen and it looks like linear algebra material.
http://en.wikipedia.org/wiki/3D_projection#Third_step:_perspective_transform

So i guess not know what i can't really do with a FPGA, am i crazy to think i will be able to make a vector matrix math in hardware?

I don't know it is really early on the thinking board but if i do get a simple video accelerator to work it would be a pretty cool senior project to make something more useful with it (multi-Vector pipe-lines and Pixel Pipe-lines).

Any thoughts?

 

[Atheus]

I have no idea, I've only done graphics in software (on the CPU), but this is a great project concept!

Just out of interest, do you plan on making an entire video card with a frame buffer and a VGA port? Or will you simply offload math to the FGPA(s), return it to the main system, then send to framebuffer? Because that might be quite slow. And you will have to write a driver for this thing, and some kind of code library to allow you to to use it from an actual C program...

Actually the more I think about it the more difficult is sounds...

 

[Lord Banshee]

IN one of the labs we actually make a simple 2D video adapter., with video ram(the frame buffer i would assume) and output via VGA 15 pin.

So it will be the whole graphics card. But it will not be for a windows or even an x86 system.
If i get it to work i plan no first
1) just have a single point file that gets displayed correctly
2) Rotating points via controller (just to double check the matrix math is correctly working)
3) Possible a "simple" api like interface with what ever CPU i use with the project. We also design a simple CPU at the end of the class so it will most likely be that one for now. But if i do decide to stick with it, i probably buy some other cheap CPU to use (non x86).

And yes the more i think about the more difficult it sounds too

 

[icarus4586]

I think what you're talking about would be doable. I'm not sure how much you know about the math required, but it sounds like the labs you're doing should prepare you pretty well.

I do think that doing it from a file is a good idea. At first I assumed that you'd be trying to stick it in a PCI slot or something. That would make it ridiculously hard, since you'd have to write a driver and design an interface, too.

It'll be interesting to see how it goes once you try it.

 

[Blundar]

Your main issue with that particular board will be bandwidth. Think about graphics cards. Putting a NV7XX (or just about any GPU for that matter) on a PCI card limits the performance of the card because the bus cannot transfer data fast enough to keep the GPU busy. Enter AGP...

With your application, in all likelyhood you're going to have a pipelined design. Key to keeping a pipelined design working at optimal speed is ... BANDWIDTH.

My advice to you would be to finish your class and then look around (or design yourself) for an inexpensive PCI or AGP based FPGA board.

 

[Lord Banshee]

Blundar,

I don't think bandwidth will be a problem because it isn't going to be something even close to what Nvidia or ATI or even VIA makes.

My design will be a firstly a simple vertex pipeline. A Voodoo 1 would probably be 10-100x better than my design. I don't see bandwidth being an problem.

If i am successful with the first design i will try to design a pixel pipe line that not not know shows a single pixel for a vertex but solid colors.

I'll keep my goals here for now . But speed isn't an issue as i am not making some FPS game using my design. Nor do i have the knowledge to create a PCI-AGP device to work with an x86 computer either.

But if you still think i will have bandwidth issues please bring them up.

Thanks,
Chris

 

[helpme]

I've never used a cyclone (I'm a Xilinx person), but you should be able to fit a VGA core that will take care of all the display stuff in there with no problem. You can get a pre-designed (free) core that will handle all of the VGA display signals. You'll just need to write the processing portions of the hardware for your "3D" display data that will feed the display driver portion.

You should have access to some onchip Block Ram, so you shouldn't have a problem with memory bandwidth or off chip components.

Do you have to use that board? Can you use an similar Spartan-3 based board? I have some sample code that was ready to go for the Spartan-3 dev boards some people at my school used.

 

[Lord Banshee]

helpme,

I already own this board listed so i will not be buying another board unless i need to. Thanks for clearing up the bandwidth thing Also i actually want to wait and build my own VGA Signal controller also, which i stated above is in one of our labs. And you are also correct about the onchip Block Ram, we will be using it as a RAM Source.

I'll probally start working on the design half-way though the class as i should know enough VHDL to do it (hopefully).. I get excited everytime i think about it and then it also dawns to me this will get 10x more complecated if i decided to take it further with shading

Thanks agian.

 

[KTL]

When you use the M4K RAM blocks, make sure you check the datasheet for the width/depth size, since there will be a limit to how many blocks you can fit alongside the rest of the VHDL codes. The M4K RAM blocks are easily created through Quartus' wizard, you don't really need to instantiate them. Of course, those RAM blocks are all dynamic, so unless you want something static, you'll need to add external memory sources like Flash or NOVRAM-type.

The Cyclone families are all CPLDs, much like Xilinx's CoolRunner series, so their compilation method will be different compared to gate-level logic devices.

 

[helpme]

The cyclone is listed as an FPGA on Altera's webpage? I thought only the MAX series of devices are CPLDs.

Banshee, you shouldn't have any problem implementing a controller on your dev board. You can even start designing the hardware now (on paper or schematic), and when you are up to speed with VHDL, you can implement the design you have already worked out.

The one thing I would recommend is to use an LCD, or crt monitor that has some protection circuitry in it that will prevent it from being overdriven. While you test your design, there's always the chance that you'll send a out of range signal to the monitor, and destroy it (if it's an old one without protection circuits).

 

[Lord Banshee]

KTL,
The Cyclone is a FPGA not a CPLD. Altera's CPLD are the MAX series. They are made no where near the same internaly.

But about the RAM blocks, yeah i most likely will not have much left to do any huge resolutions or a ton of objects. Not a problem this is just going to be a simple test.

But yeah there is a ton more i need to learn before i start.

Thanks

*edit*
helpme,
I am using a Dell 2405, so i hope it has that protection circuitry. That wouldn't be good if i destroy it by a mistake in math....

Yeah i was planning on working on a schematic till i get to speed with VHDL.

I am sure i will be bringing this topic back up again and again for some help if i need it

 

[helpme]

The warning only applies to older CRTs, the A/D in the LCDs will probably just ignore the signal if it's out of range. At worse, you just get garbage on the screen, it won't break anything.

 

[Lord Banshee]

Good to know

thanks

 

[KTL]

Doh...you're both right, the Cyclones are FPGAs, I was thinking about the MAX parts, which are CPLDs. After 5 years of using FPGA/CPLD devices, you'd think I'd remember.

If you can think of how the circuit would look in gate-level logic, then VHDL representation is pretty straightforward. You can certainly add gates to the schematics in Quartus II, there are even some Megacores that you can specify and customize to your needs. The actual VHDL source codes are pretty simple, it's the testbench that consumes most of the time, since you can simulate in 1) behaviorial, 2) post-synthesis, and/or 3) post-route environments.