Discussion Qualcomm Snapdragon Thread

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Jul 27, 2020
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$1100. That's bullshit from ASUS.

I think it's fine given the price bracket is <$700. But I definitely don't understand why keep a 40 TOPs NPU with single-channel memory.

QCOM will really need to push their OEMs to offer cheap designs with this. Otherwise it's another huge failure like X Elite.

They save a lot in platform costs but it's definitely a puzzling decision.
Yes. QCOM is ignoring our posts despite their staff being registered here as members.

This is not good. Purwa is only acceptable in $550 laptops. Max.
 

FlameTail

Diamond Member
Dec 15, 2021
3,755
2,203
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I think you guys are overreacting about the "single-channel memory" (aka 64 bit memory bus).

Considering that Purwa has less than half of the GPU performance of Hamoa, and about half the CPU multicore performance of Hamoa, it makes sense to cut the memory bus also in half. (Purwa still keeps the same 6 MB capacity SLC as Hamoa).

In fact, I have often wondered why Intel/AMD don't use single-channel memory for their low end parts.

Eg:
Meteor Lake-H = 6P+8E+2LPE + 8 Xe1
Meteor Lake-U = 2P+8E+2LPE + 4 Xe1

MTL-U has about half the CPU and half the GPU of MTL-H. Why not give MTL-U half the memory bus?

As for the NPU, I don't think the 64 bit memory bus is going to be problem. I doubt these puny <50 TOPS NPUs can saturate a 64 bit LPDDR5X-8533 memory bus.

Snapdragon 8G345 TOPS
Dimensity 930048 TOPS
Snapdragon 8G470+ TOPS*
Dimensity 940067 TOPS*
*rumoured

And all these mobile SoCs have 64 bit memory buses.

My only issue with this part is the pricing. It should belong in <$800 laptops.
 

gdansk

Platinum Member
Feb 8, 2011
2,833
4,211
136
In fact, I have often wondered why Intel/AMD don't use single-channel memory for their low end parts.
They do. But these chips (Alder Lake N and Mendocino) are slower and cheaper.

Still amazed Qualcomm is trying to compete with M1 and Phoenix - which are both in <650$ laptops - with such a weirdly cut down chip.
 

Ghostsonplanets

Senior member
Mar 1, 2024
679
1,099
96
I think you guys are overreacting about the "single-channel memory" (aka 64 bit memory bus).

Considering that Purwa has less than half of the GPU performance of Hamoa, and about half the CPU multicore performance of Hamoa, it makes sense to cut the memory bus also in half. (Purwa still keeps the same 6 MB capacity SLC as Hamoa).

In fact, I have often wondered why Intel/AMD don't use single-channel memory for their low end parts.

Eg:
Meteor Lake-H = 6P+8E+2LPE + 8 Xe1
Meteor Lake-U = 2P+8E+2LPE + 4 Xe1

MTL-U has about half the CPU and half the GPU of MTL-H. Why not give MTL-U half the memory bus?

As for the NPU, I don't think the 64 bit memory bus is going to be problem. I doubt these puny <50 TOPS NPUs can saturate a 64 bit LPDDR5X-8533 memory bus.

Snapdragon 8G345 TOPS
Dimensity 930048 TOPS
Snapdragon 8G470+ TOPS*
Dimensity 940067 TOPS*
*rumoured

And all these mobile SoCs have 64 bit memory buses.

My only issue with this part is the pricing. It should belong in <$800 laptops.
As I said, I think it's fine. Even if puzzling given the 40 TOPs NPU still being presented. But, as you said, the price is an issue. This SoC needs to appear on <$700 laptops and need wide availability on multiple markets. Let's see what QCOM will announce at IFA.

It's probably the best shot Windows on Arm and Snapdragon X platform have at having a mainstream presence and creating mindshare.
 
Jul 27, 2020
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If you think the engineers who designed the core have anything to say in these matters
An engineer can and should put their foot down.

"The mere suggestion of bottlenecking my chip's performance is a travesty! I will simply not have it!"

"I will not let my chip be used in this inhumane manner!"

"I did not waste years of my life just so consumers get dissatisfied with MY chip!"

"Sure, you can do that to my chip. And then deal with what happens next!"

"Would you hobble your own child, for example, by forcing them to walk on one shoe only?"
 
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Doug S

Platinum Member
Feb 8, 2020
2,698
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If you think the engineers who designed the core have anything to say in these matters... Didn't a marketing guy "correct" some words from GW3 during HotChips?

This.

The marketing guys are the ones who set prices, decide on the number of SKUs they want, and if they believe the best way to segment the markets means disabling one of the memory channels on some offerings that'll be what gets done. If GW III and co don't like it, there isn't anything they can do about it except quit. That's the reality of all big companies. If they didn't want to have to deal with that sort of thing they would have turned down Qualcomm's offer and Nuvia would still be an independent company.

I don't know why people were expecting anything different, or expecting that the Qualcomm people registered here are going to reply to random queries about stuff like that over which they have zero control. They may not like it any better than those complaining here, but what good would do them to make such feelings public and give their boss cause to call them in for the old "we're all a team here, we need everyone rowing in the same direction etc." speech.
 
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POWER4

Member
May 25, 2024
54
28
51
The marketing guys are the ones who set prices, decide on the number of SKUs they want, and if they believe the best way to segment the markets means disabling one of the memory channels on some offerings that'll be what gets done. If GW III and co don't like it, there isn't anything they can do about it except quit. That's the reality of all big companies. If they didn't want to have to deal with that sort of thing they would have turned down Qualcomm's offer and Nuvia would still be an independent company.
This is a bit simplistic. There are many, many people involved in bringing any product to life. Engineers, programmers, product managers, financial, sales, and... marketing. All of which have their inputs, but still each to his own. I don't think a "marketing" guy is deciding on the number of memory channels.

X1P-42 is not a product in a vacuum. It is part of a roadmap. I'm sure early on during development, GW sat down with members of the aforementioned teams to discuss this product. Certainly, they had a price range in mind, along with many wishes and KPIs, all to cater to a target audience. And, from an engineering point of view, he should have enjoyed plenty of space to decide how to achieve it. Maybe he was asked too much with too little? Maybe. But for all we know, he and his team know how to balance stuff.

Each company has its own product strategy and segmentation. Apple has, at most, eight SKUs per generation. Intel had 30+ for mobile Raptor Lake. AMD always had a strong focus on bringing solid iGPUs. Maybe you felt compelled by that. I wasn't. Different targets, different compromises. See?
 

SteinFG

Senior member
Dec 29, 2021
616
726
106
In fact, I have often wondered why Intel/AMD don't use single-channel memory for their low end parts.

Eg:
Meteor Lake-H = 6P+8E+2LPE + 8 Xe1
Meteor Lake-U = 2P+8E+2LPE + 4 Xe1
Because 2 P-cores, 8 E-cores, 2 LPE-cores, 4Xe cores, is a ton of cpu+gpu cores to feed with 64-bit wide LPDDR5 interface. It's similar to 128-bit LPDDR4-3200, which was standard in... 2019-2020. In fact, Intel makes 64-bit wide CPUs - N100, N300, and their derivatives. They just have less of everything: 4-8 E-cores and a small iGPU. Same with AMD. 7320U and 7520U are 64-bit only, they have 4 Zen2 cores and small iGPU. Purwa will have similar bandwidth to those chips, and most likely perform similar in a lot of multicore tests.
 

FlameTail

Diamond Member
Dec 15, 2021
3,755
2,203
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If Purwa has the same speed LPDDR5X-8488 as Hamoa does, with a 64 bit memory bud that results in 67 GB/s of memory bandwidth (which is similar to the OG Apple M1 - 68 GB/s).
 

FlameTail

Diamond Member
Dec 15, 2021
3,755
2,203
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Because 2 P-cores, 8 E-cores, 2 LPE-cores, 4Xe cores, is a ton of cpu+gpu cores to feed with 64-bit wide LPDDR5 interface. It's similar to 128-bit LPDDR4-3200,
Today LPDDR5X-8500 is the standard, not LPDDR5-6400.
Purwa will have similar bandwidth to those chips, and most likely perform similar in a lot of multicore tests.
According to Wccftech's leak, X1P-42-100 scores ~650 points in CB2024 multicore, and ~11500 points in Geekbench 6 multicore. That's similar performance to Apple M3 or a Ryzen 8640U.
 

Doug S

Platinum Member
Feb 8, 2020
2,698
4,577
136
This is a bit simplistic. There are many, many people involved in bringing any product to life. Engineers, programmers, product managers, financial, sales, and... marketing. All of which have their inputs, but still each to his own. I don't think a "marketing" guy is deciding on the number of memory channels.

X1P-42 is not a product in a vacuum. It is part of a roadmap. I'm sure early on during development, GW sat down with members of the aforementioned teams to discuss this product. Certainly, they had a price range in mind, along with many wishes and KPIs, all to cater to a target audience. And, from an engineering point of view, he should have enjoyed plenty of space to decide how to achieve it. Maybe he was asked too much with too little? Maybe. But for all we know, he and his team know how to balance stuff.

Each company has its own product strategy and segmentation. Apple has, at most, eight SKUs per generation. Intel had 30+ for mobile Raptor Lake. AMD always had a strong focus on bringing solid iGPUs. Maybe you felt compelled by that. I wasn't. Different targets, different compromises. See?

I wasn't implying that marketing alone has sole authority. But they do projections and determine what they think will maximize revenue with the proper mix of SKUs. They aren't saying "hey disable one memory channel" but they are saying "we want SKUs in this price band, but to avoid cannibalizing our higher price bands the performance of these cheaper SKUs needs to be limited in some way". So they aren't making the call "disable one memory channel" vs "cut clock rate by 700 MHz" vs "disable half the cache" but they are making the "we need to make this SKU worse enough that we can charge $100 less for it and customers won't choose this instead of the higher priced option because the performance is too similar".

Everyone does this. Look at the range of clock speeds (at similar TDPs) on Intel and AMD CPUs using the same cores. They aren't binning down that low in reality, that's a marketing driven decision. Look at Apple with the "missing GPU and CPU core" in their cheaper SKUs. Sure maybe they have a couple percent of chips that fail in one or the other core so that helps them recover 1-2% yield, but few people would really object to losing one core out of a dozen so almost everyone would take that choice to save a bit of money if that was the only cost. But it isn't - they generally pair it with a smaller RAM/NAND config which matters to a lot more people. That's not an engineering decision, that's purely driven by the needs of marketing. Even if the marketers aren't the ones deciding on the memory configs, just saying "we need the cheaper option to not be so close to the step up option it cannibalizes sales of that step up option".
 

LightningZ71

Golden Member
Mar 10, 2017
1,778
2,134
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In relation to the above post, look at how AMD groups their last three generations of mobile SoC. Their 8 core SoCs got the full iGPU config and their 6 core SoCs got the cut down iGPU. While AMD was perfectly capable of recovering SoCs that only had a below spec core as a 6 core Soc with a full iGPU, they knew that most people would just buy that instead of the higher priced 8 core SoCs with full iGPU. A notable exception was a Lenovo specific SKU that had a less disabled iGPU than the rest.
 

Doug S

Platinum Member
Feb 8, 2020
2,698
4,577
136
In relation to the above post, look at how AMD groups their last three generations of mobile SoC. Their 8 core SoCs got the full iGPU config and their 6 core SoCs got the cut down iGPU. While AMD was perfectly capable of recovering SoCs that only had a below spec core as a 6 core Soc with a full iGPU, they knew that most people would just buy that instead of the higher priced 8 core SoCs with full iGPU. A notable exception was a Lenovo specific SKU that had a less disabled iGPU than the rest.

That's the other game they can play. They could say "OK Lenovo we'll sell you a special SKU that removes some of the hamstringing our lower end chips normally get, in exchange for a promise that they are only used in laptops selling above a particular price". That way they avoid the cannibalization issue, at least for themselves - it isn't their problem if Lenovo cannibalizes its own product lines.
 

POWER4

Member
May 25, 2024
54
28
51
I wasn't implying that marketing alone has sole authority. But they do projections and determine what they think will maximize revenue with the proper mix of SKUs. They aren't saying "hey disable one memory channel" but they are saying "we want SKUs in this price band, but to avoid cannibalizing our higher price bands the performance of these cheaper SKUs needs to be limited in some way". So they aren't making the call "disable one memory channel" vs "cut clock rate by 700 MHz" vs "disable half the cache" but they are making the "we need to make this SKU worse enough that we can charge $100 less for it and customers won't choose this instead of the higher priced option because the performance is too similar".

Everyone does this. Look at the range of clock speeds (at similar TDPs) on Intel and AMD CPUs using the same cores. They aren't binning down that low in reality, that's a marketing driven decision. Look at Apple with the "missing GPU and CPU core" in their cheaper SKUs. Sure maybe they have a couple percent of chips that fail in one or the other core so that helps them recover 1-2% yield, but few people would really object to losing one core out of a dozen so almost everyone would take that choice to save a bit of money if that was the only cost. But it isn't - they generally pair it with a smaller RAM/NAND config which matters to a lot more people. That's not an engineering decision, that's purely driven by the needs of marketing. Even if the marketers aren't the ones deciding on the memory configs, just saying "we need the cheaper option to not be so close to the step up option it cannibalizes sales of that step up option".
I pretty much agree, with some exceptions.

First, I would not say it is a "marketing" decision. It is a business decision made by different teams. Still, if pressed, I would probably call it a product management decision. Second, I do think it is an, at least partially, engineering decision on where and how you will cut down, while keeping the KPIs important to the target audience.

Finally, I'm not sure the following idea is very accurate (I know it is not literal)
"we need to make this SKU worse enough that we can charge $100 less for it and customers won't choose this instead of the higher priced option because the performance is too similar".
This is not how companies like AMD, Intel, and Qualcomm tend to operate. Maybe we are too used to Apple's obscene price anchoring, but when you have to sell chips to cheap OEMs, price becomes a matter of survival. Obviously they would love for you to choose the higher-priced one, but reality is not always that good.
 

FlameTail

Diamond Member
Dec 15, 2021
3,755
2,203
106
Two things that have been on my mind lately:

[1] X Elite doesn't have E-cores. We have talked about how that's hurting their efficency in comparison with Apple. In a hypothetical scenario, if both Apple and Qualcomm didn't have E-cores, Qualcomm would still be the one hurting more. Why? Because Windows has so much cruft (background processes) running all the time, compared to MacOS.

[2] So apparently Qualcomm uses a different scheduling behaviour for X Elite compared to what Apple's doing with their chips.

So in Apple M chips, if you load two threads to the CPU, the scheduler tries to keep both threads within a single cluster. This is great for efficiency, because only a single cluster is active, and the rest are power gated.

In Snapdragon X Elite, if you load two threads to the CPU, the scheduler loads each thread to separate clusters.This maximises the amount of L2 cache a thread can access, hence maximising the performance.

Interesting difference. (This is second hand information though, so it might be incorrect).
 
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