Discussion Qualcomm Snapdragon Thread

[soresu]

Qualcomm's Adreno GPU is interesting in that it uses a "wide and slow" approach compared to others who are doing "narrow and fast".

Exynos 2400 = 768 ALU
SD 8G3 = 1792 ALU

That assumes all ALU's are created equal - Exynos is using AMD RDNAx based µArch so it's likely got all the bells and whistles of a full PC GPU in feature set similarly to the Switch GPU albeit far more recent.

Also Samsung produce far less SoC's than QC does as they mostly just produce for themselves these days (vs QC who produce for everyone else that doesn't use Mediatek), so they may be cost cutting by making smaller GPU's.

 

[FlameTail]

Compared to RDNA for example, Adreno may have more ALU, but it also runs at higher clockspeeds.

We know higher clocks are not coming for free. It requires more transistors, and hence takes up more area.

So although Exynos 2400 GPU may have less ALUs than 8G3, I am guessing the die is similar as Exynos runs those ALUs at higher speeds.

 

[FlameTail]

That assumes all ALU's are created equal - Exynos is using AMD RDNAx based µArch so it's likely got all the bells and whistles of a full PC GPU in feature set similarly to the Switch GPU albeit far more rec

3DMARK WLE
8 Gen 2: 22 FPS @7.1W
X Elite: 44 FPS @31W

So X Elite has exactly double the GPU.
performance of the 8 Gen 2. This fits with the rumour that X Elite has the same GPU architecture as 8 Gen 2, but scaled up by 2x.

That makes sense looking at the performance, but not at the power consumption.

If X Elite GPU is 2x the ALUs of the 8 Gen 2 GPU, then why is it consuming 4x the power?

Yes, the 8 Gen 2 and X Elite power consumption figures are coming from different sources (Geekerwan vs Qualcomm), but that does not explain the huge disparity.

So I see two potential explanations:

1) X Elite is not the 8 Gen 2 GPU, with double the ALU count. After all, this only a rumour. May be it is the 8 Gen 2 GPU, but with 2x the clock speed? That explains the 4x increase in power consumption, despite only 2x increase in performance. I have explained this hypothesis several times in this thread discussion

or.....

2)

That assumes all ALU's are created equal - Exynos is using AMD RDNAx based µArch so it's likely got all the bells and whistles of a full PC GPU in feature set similarly to the Switch GPU albeit far more recent.

This.

Perhaps the 8 Gen 2 GPU does not have the PC-class "features'. So they added these to the X Elite GPU, while also doubling (2x) the ALU count, which may explain the 4x jump in power consumption...

 

[soresu]

Perhaps the 8 Gen 2 GPU does not have the PC-class "features'. So they added these to the X Elite GPU, while also doubling (2x) the ALU count, which may explain the 4x jump in power consumption...

No more likely than Apple doing the same for Mx series GPUs which (as far as I am aware) we know to be deficient in absolute feature set vs AMD and nVidia alternatives.

Metal means that Apple users aren't ever going to know the difference, but trying to implement all the current OGL and Vulkan bells and whistles on Asahi Linux is probably never going to be fully viable.

I'd be surprised if the same wasn't true about SDXE.

They will implement DX12 gaming features at a minimum, but beyond that I would expect problems with absolute compatibility to OGL codebases - at best we will likely suffer emulation of certain features on legacy software that has no native WoA port.

 

[FlameTail]

New Snapdragon leak just dropped!

That 8G5 uses same N3E as 8G4 is bizarre. May be a typo. It should be N3P, right.

Also this confirms previous rumour that 2nd gen Oryon/Nuvia core is named Pegasus.

 

[Tigerick]

New Snapdragon leak just dropped!
View attachment 93793
That 8G5 uses same N3E as 8G4 is bizarre. May be a typo. It should be N3P, right.

Also this confirms previous rumour that 2nd gen Oryon/Nuvia core is named Pegasus.

View attachment 93794
View attachment 93795

Yeah, 8G5 is based on N3P, Samsung will try their own with SF2. Also 8G5 might be the first SoC to employ LPDDR6

 

[FlameTail]

Also 8G5 might be the first SoC to employ LPDDR6

I believe so.

 

[FlameTail]

Knowing this, what can we speculate about the 2nd generation Snapdragon X Elite?

 

[Tigerick]

I believe so.

And have you wonder what is Pegasus core used for?

 

[FlameTail]

And have you wonder what is Pegasus core used for?

Is that a trap question?

 

[FlameTail]

What is Qualcomm'a work on chiplets?

As nodes become progressively more expensive, and the incoming reticle size halving with High-NA EUV, chiplets are becoming more and more important.

All the big 3 players in the PC industry have some degree of work in chiplets. Intel and AMD are already shipping products with chiplets. Nvidia products remain monolithic for now, but they have published a ton of research on chiplet GPUs, indicating they will move yo chiplet GPUs in the future.

Even Apple has some limited progress on chiplets, in the form of M Ultra chips which bond two M Max chips together.

Qualcomm used to be a primarily mobile focused company, and for that segment chiplets won't matter atleast for the foreseeable future. Mobile SoCs are very small in terms of die size, so they are better able to take the hit from exponentially increasing node costs. Also, power efficiency is paramount in mobile chips, and we know chiplets is a gut wrench for power efficiency.

But Qualcomm is moving to the PC space, and they are making big SoCs.

 

[gdansk]

Simple solution: stay under 200 mm sq monolithic.
You don't need more than that unless you want to compete with Nvidia.

 

[FlameTail]

Simple solution: stay under 200 mm sq monolithic.
You don't need more than that unless you want to compete with Nvidia.

Who is that advice for

 

[gdansk]

Who is that advice for

It isn't advice, it's what will happen for some time.
Multichip solutions needless complication for a design that needs to prove itself first.

 

[FlameTail]

Simple solution: stay under 200 mm sq monolithic.
You don't need more than that unless you want to compete with Nvidia.

Well, stuff like Strix Point is >200 mm²

 

[FlameTail]

Any SoC with a big iGPU with >128 bit memory bus will we be >200 mm².

 

[gdansk]

Any SoC with a big iGPU with >128 bit memory bus will we be >200 mm².

Does Qualcomm have any plans for those?
For an unproven product line.

 

[Doug S]

Simple solution: stay under 200 mm sq monolithic.
You don't need more than that unless you want to compete with Nvidia.

You can go up to 429 mm^2 and fit inside a high NA reticle. It is only really big chips that will HAVE to go to chiplets. Unless Qualcomm plans to enter the server CPU market I don't think they will need to go chiplet.

Intel and AMD are doing it on smaller chips because they have a huge number of SKUs to serve every possible market. They aren't using chiplets for mobile CPUs because they are big, they are using it because they are selling 50+ different SKUs just for laptops. Heck maybe 100+.

They're also using it to make stuff like AMD's I/O chip in an older process, or Intel to have TSMC cover up for their lack of capacity until they get all those fabs they have on the drawing board actually built.

 

[gdansk]

You can go up to 429 mm^2 and fit inside a high NA reticle. It is only really big chips that will HAVE to go to chiplets. Unless Qualcomm plans to enter the server CPU market I don't think they will need to go chiplet.

Intel and AMD are doing it on smaller chips because they have a huge number of SKUs to serve every possible market. They aren't using chiplets for mobile CPUs because they are big, they are using it because they are selling 50+ different SKUs just for laptops. Heck maybe 100+.

They're also using it to make stuff like AMD's I/O chip in an older process, or Intel to have TSMC cover up for their lack of capacity until they get all those fabs they have on the drawing board actually built.

I wasn't thinking of reticle limit but cost. If they do make a bigger chip on N3, it should be monolithic as well. But living as a second-class citizen in the Windows world with real competition on pricing from Intel/AMD they should move cautiously on making big dies.

 

[FlameTail]

I wasn't thinking of reticle limit but cost. If they do make a bigger chip on N3, it should be monolithic as well. But living as a second-class citizen in the Windows world with real competition on pricing from Intel/AMD they should move cautiously on making big dies.

Take a fuse and start fusing off all the defective areas in the dies!

SKU segmentation!

 

[FlameTail]

I wasn't thinking of reticle limit but cost. If they do make a bigger chip on N3, it should be monolithic as well. But living as a second-class citizen in the Windows world with real competition on pricing from Intel/AMD they should move cautiously on making big dies.

I would like them to make a Strix Halo kind of SoC.

Not in this first generation though. Maybe in the 2nd or 3rd generation of Snapdragon X processors. Especially since the GPU drivers and game compatibility will take some time to work out.

 

[FlameTail]

Windows 11 AI super resolution scaling for all apps previewed in the latest insider build

Windows 11 24H2 Preview Build hides a built-in upscale option potentially for all apps and games

www.tomshardware.com

For this OS-lever super-resolution to work, the system needs a processor with NPU cores, like the upcoming Intel Arrow Lake and Lunar Lake CPUs or have GPUs with tensor cores.

This is great news for the Snapdragon X Elite.

It means that we can enjoy resolution upscaling on Snapdragon X Elite devices, while Qualcomm doesn't have to put in the effort to develop a DLSS/FSR alternative.

It also means that the powerful 45 TOPS NPU is put to good use.

 

[FlameTail]

https://x.com/unixterminal/status/1758018147771138186?s=20

Allegedly, you cannot install the new Apple Music for Windows, on WoA devices. It's only for x86.

 

[SteinFG]

https://x.com/unixterminal/status/1758018147771138186?s=20

Allegedly, you cannot install the new Apple Music for Windows, on WoA devices. It's only for x86.

Because there's no native windows-on-arm build, not a mistery

 

[Doug S]

I wasn't thinking of reticle limit but cost. If they do make a bigger chip on N3, it should be monolithic as well. But living as a second-class citizen in the Windows world with real competition on pricing from Intel/AMD they should move cautiously on making big dies.

Cost depends on how much they can bin partially working parts, if they have SKUs that can use fewer CPU or GPU cores, less L3, etc. There's also going to be a crossover where making dies smaller increases per sq mm cost due to handling/testing/packaging overhead on more units. I have no idea where that crossover is but for a typical ~150 mm^2 laptop/desktop SoC it might make sense to break it into 2 or 3 pieces but does it make sense to break it into 8 or 12 pieces? I'm skeptical there.