Nope.I hope this marks the beginning of sane power limits in windows laptops
Not mutually exclusive.Don't get me wrong, nothing wrong with a DTR, but at least offer the option to reign in power use to claw back some battery life.
This is interesting — I wonder how much it differs depending on the setup though. Having a small L0 to buoy you against a higher latency L1L0 caches are a waste of energy.
They have another die coming.Don't act so smug. QC is making big mistakes. You don't conquer a market with premium devices. You do so with a broad range of price points from $300 to $999. More than that is for professionals or gamers. Microsoft/QC are dumb to think that people will max out their credit cards to afford AI stuff. The average person does not have to lie so much like salespeople/sales engineers/marketing folks/scummy businessmen that they need to keep a database of their lies in their head to avoid their lies getting caught so there isn't enough space in their heads for the mundane stuff like remembering appointments or retaining important details from their emails that they read already. Only these people have a use case for Microsoft Recall at a $1000+ price point. Or maybe imposters who will try to act like executives who know what they are doing.
i or d?Having a small L0 to buoy you against a higher latency L1
This is interesting — I wonder how much it differs depending on the setup though. Having a small L0 to buoy you against a higher latency L1
Established convention.What I don't get why it should be called an L0
In other words, L0 is a kind of a micro-op cache?The likes of Krait had tiny L0i's and all.
Sort of, Krait L0 didn't store decoded uops, just instructions.In other words, L0 is a kind of a micro-op cache?
That's because uOp caches really aren't that, they store decoded uops.Google isn't much help and it seems most CPU designs don't denote a micro-op cache as L0.
Too tiny to make any real impact with modern code/data footprints.Why that makes it power wasteful like Gerard is saying
Micro-op caches tend to be after L1 because the micro-op split obviously operates on fetched instructions. Also micro-op caches are not like traditional caches. I'm sure you should find correct information on Google (and surely in filed patents).In other words, L0 is a kind of a micro-op cache?
Google isn't much help and it seems most CPU designs don't denote a micro-op cache as L0.
Predecode windows are on ARM things too.Also L1 icache now often contain extra information (IIRC on x86 it has extra bits to indicate instruction boundaries).
Yes, that was somewhat useful for 32-bit Arm.But not for 64-bit Arm. (Only talking in the context of the x86 instruction boundaries example I gave. There's a lot of other useful information one can store in Icache, I guess many patents exist that give hints.)Predecode windows are on ARM things too.
It's not new.
I read something about filter cache and data filter cache. Any production CPUs implemented that?I guess many patents exist that give hints.
He’s not really an honest actor.Hmm.
By that standard, Altra never hit GA, and therefore doesn't exist.
I don't care enough about AMD to hate them. (Or Intel, ARM, Nvidia... I care about IBM stuff a fair bit, which is why I do hate IBM.)
You seem upset though.
General Availability.What is GA?
lol"HPC doesn't count because reasons"
"When I said everyone I meant everyone but HPC"
Well I have evidence that Neoverse-V3 is 0.08mm2 in an implementation on TSMC N4 capable of achieving 6GHz, does iso-clock performance 35% higher than Zen7, and dissipates 110mW in that configuration! You can only see it if you give me money tho.
For it to be useful, it needs a good hit rate, which means its size matters. It will ve a guaranteed VIVT structure since it lives before the L1TLB. So you need to do PA aliasing checks on it or hold the PA inside the structure so it can be coherently managed. You can get clever and build mechanisms to help it but you will never approach the hit rate of a 64, 80, 96, or 128KB cache. Hence the comment about wasteful energy and area. And it also needs to forward data to all the same structures that the L1 cache also forwards, and you are widening every forwarding mux. Is it inclusive with whats in L1 or L2? I can ask a million questions about how to handle this or that but no simple answer come to mind.In other words, L0 is a kind of a micro-op cache?
Google isn't much help and it seems most CPU designs don't denote a micro-op cache as L0.
There's even crap being taught at reputable universities like the following:
View attachment 99793
I think the main characteristic of an L0, from what I can understand, is that it has a latency of 1 cycle or less and can provide 128 bytes of cached data or decoded instructions.
Why that makes it power wasteful like Gerard is saying, is unclear to me.
thank you for the brilliant explanationFor it to be useful, it needs a good hit rate, which means its size matters. It will ve a guaranteed VIVT structure since it lives before the L1TLB. So you need to do PA aliasing checks on it or hold the PA inside the structure so it can be coherently managed. You can get clever and build mechanisms to help it but you will never approach the hit rate of a 64, 80, 96, or 128KB cache. Hence the comment about wasteful energy and area. And it also needs to forward data to all the same structures that the L1 cache also forwards, and you are widening every forwarding mux. Is it inclusive with whats in L1 or L2? I can ask a million questions about how to handle this or that but no simple answer come to mind.