I'm not sure how to respond here. I'm thinking Qualcomm should not pursue chiplets. They apparently (from the slides) get plenty of performance at the die sizes they are using now. With new nodes available and some more die area for future chips it should be enough to stay competitive and low enough cost even on N3. What do they gain from it? If they want more cores and more GPU/NPU performance they can simply make a bigger die beyond the 200mm² limit I suggested. But it had better be good - because that's gonna be more expensive than Intel and AMD parts (Qualcomm margins lol).Cost depends on how much they can bin partially working parts, if they have SKUs that can use fewer CPU or GPU cores, less L3, etc. There's also going to be a crossover where making dies smaller increases per sq mm cost due to handling/testing/packaging overhead on more units. I have no idea where that crossover is but for a typical ~150 mm^2 laptop/desktop SoC it might make sense to break it into 2 or 3 pieces but does it make sense to break it into 8 or 12 pieces? I'm skeptical there.
Disaggregation seems anti-thetical to Snapdragon. But who knows. Maybe they link two together for even more performance.
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