The memory frequency is an external bus. As the bus cycles faster and faster, it has to delay slightly more in order for the memory to be able to respond. A certain amount of time has to pass for the transistors to function, no matter how fast the bus is running, and precharges and stuff take the same amount of time no matter what the bus speed (the timings can be changed, but memory can only handle a certain rate).
So for example, at 100MHz, a 1 cycle delay is 1 unit of time. At 200MHz, a 2 cycle delay is also 1 unit of time. The bus has to wait more cycles. Increasing the bus speed doesn't actually increase the ability for the accesses to happen faster, only the data transfer once the access has started. That's why burst transfers became important, no matter how fast the memory bus was, if each access required the same timing delays, the data transfers were slowed down. With burst transfers, all those extra accesses were eliminated, and the data transfer just streamed through without delays other than the first one.