SDRAM has a 64-bit parallel bus; each word is 64-bits, and in clock cycle N it transfers word M, in clock cycle N+1 it transfers M+1, etc. DDR SDRAM differs from SDRAM largely that it send data on the rising and falling edges of each clock signal, so it has twice the effective bandwidth.
RDRAM has a 16-bit serial bus...IIRC, each word is 8-bits, so it takes 8 clock cycles to transfer the entire word (the bits get shifted into a shift register in the memory controller to parallelize the data). In addition, since it has a 16-bit bus, it can transfer the bits of 16 words at one time. So in clock cycle N it transfers bit 0 of the 16 words, in clock cycle N+1 it transfers bit 1 of the 16 words, up to bit 7 of the 16 words in clock cycle N+7. of course, RDRAM is double-data-rate like DDR SDRAM, so it actually transfers data on clock cycles N, N+1/2, N+1, N+3/2, etc.
The maximum bandwidth available by PC2100 DDR SDRAM is 133MHz * 2 (double-data-rate) * 64-bits/cycle = 2133 MB/sec. The maximum bandwidth available by PC800 RDRAM is 400MHz * 2 (double-data-rate) * 16-bits/cycle = 1600 MB/sec. Of course, these are just peak figures....neither DRAM technology spends all of its time transferring data. For example, to complete a memory read, DRAM has to send the address and control information across the FSB (1 cycle), latch and decode the control information (2 cycles), wait for the CAS latency (2-3 cycles) and possibly the RAS and precharge latencies (4-6 cycles). Then DDR SDRAM can begin transferring data twice per clock cycle. If no memory operations run concurrently, the maximum bandwidth available with DRAM is only around 1/3-1/4 of the maximum bandwidth. But a good memory controller design with out-of-order execution, large buffers, and concurrency can attempt to reach a effective bandwidth much closer to its theoretical bandwidth.
Personally, I think most of those people saying "RDRAM is the future" or "DDR SDRAM is the future" really haven't the faintest clue about the engineering advantages and disadvantages of either platform. Regarding the specific DRAM types, we've seen all too often in the past that superior technology can loose to inferior technology that carries wider availability and a lower price. And I highly doubt that anybody that vocal about RAM standards are actively involved in decided which platform will be the future standard. Many people say that serial busses will become absolutely necessary for future high speed busses...I think that's a little short sighted. Serial busses definitely has a major advantage over parallel busses because they can be clocked higher; in a parallel bus, all the bit lines and the clock line has to be perfectly (or very close to it) synchronized with each other, which can be difficult for high speed busses. Bus that doesn't mean that serial busses is the only way to accomplish high speed busses, it just means that it is generally easier to accomplish. Besides, such an argument is also ignoring a fundamental concept of computer science and engineering, that of the recycling of concepts. Technology that may become obsolete tomorrow may again become necessary in the future.
I may add to this later, I have to go to class.