Question Raptor Lake - Official Thread

[Hulk]

Since we already have the first Raptor Lake leak I'm thinking it should have it's own thread.
What do we know so far?
From Anandtech's Intel Process Roadmap articles from July:

Built on Intel 7 with upgraded FinFET
10-15% PPW (performance-per-watt)
Last non-tiled consumer CPU as Meteor Lake will be tiled

I'm guessing this will be a minor update to ADL with just a few microarchitecture changes to the cores. The larger change will be the new process refinement allowing 8+16 at the top of the stack.

Will it work with current z690 motherboards? If yes then that could be a major selling point for people to move to ADL rather than wait.

 

[Hulk]

In terms of die area, 12P + 16E = 8P + 28.4E using current RPL dimensions.

There wouldn't be much performance difference in lightly threaded loads and in heavily threaded ones 8P + 28.4E would be more performant and more efficient.

Such a part running at a relatively sedate 5GHz/4GHz would score almost 50,000 in CB R23 MT.

 

[DrMrLordX]

In terms of die area, 12P + 16E = 8P + 28.4E using current RPL dimensions.

Intel doesn't have any Meteor Lake chiplets that they've demoed that would allow them to produce such a core configuration. They do have a 6P + 8e chiplet they've already shown to the public.

 

[Kocicak]

What it the core numbering on Raptor lake CPUs, by that I mean where is physically located core of specific number on the die?

I would like to try enable one or two more cores to run at higher frequency, and would like to start with the cores close to the two designated cores, hoping that they could be higher quality too.

Using distant cores would be good for heat dissipation though.

 

[nicalandia]

What it the core numbering on Raptor lake CPUs, by that I mean where is physically located core of specific number on the die?

Core 0 to 7 are P Cores. 8 to 15 are e Cores, Cores 16 to 31 are just virtual cores residing on P cores, for example, number 16th core is actually a Virtual Core residing on P core 0

 

[Carfax83]

https://www.reddit.com/r/intel/comments/xu36jj

From that discussion, it seems the contact frame mainly benefits AIO cooler setups.

I bought the Thermalright version from Amazon so I will be installing it when I get my motherboard.

Don't look for detailed tests from me on it though. I'm a one and done sort of dude 😎

 

[Hulk]

I did a stupid thing. For some reason my system was resetting anytime the CPU pulled about 250 or more Watts. My "old" power supply was a 460W Seasonic fanless, surely capable of this much power with iGPU right? So I figured there was something wrong with it and bought a Seasonic TX-750 Platinum. As you can see in my new updated signature.

As I was installing the new PS I noticed only one 8 pin power connector installed! My old 12700K never pulled enough power for the second cable so to have less cable clutter I never installed it! Stupid me! I'm too old for mistakes like this.

Thought about returning the TX-750 but it's just so nice, runs fanless in hybrid mode, 12 year warranty, and of course is more efficient than my old "gold" rated one that I've decided to keep it. I'll keep the FL460 around as a spare I guess.

Just posting in case someone else has this issue. But I don't think anyone here is dumb enough to miss that like I did!

 

[Carfax83]

Here's a guy that installed it on a 12900K with an air cooled heatsink (unfortunately he doesn't specify which one but I suspect it's a Noctua NH-D15 based on the mounting bracket) but he claimed it dropped his temps by 9 degrees!

 

[Hulk]

Intel doesn't have any Meteor Lake chiplets that they've demoed that would allow them to produce such a core configuration. They do have a 6P + 8e chiplet they've already shown to the public.

Yes, of course. Just making a hypothetical argument.

 

[igor_kavinski]

Just posting in case someone else has this issue. But I don't think anyone here is dumb enough to miss that like I did!

It's actually dumb programming of the mobo BIOS not to warn at POST that the CPU may not get enough power. It already knows what model the CPU is.

 

[Grimnir]

Sounds like you admit there's an issue. If one has to remove the cooler to check for paste coverage the first time, how do you know you got it right the second time, or the third time without pulling the cooler again? Every review of these frames shows a benefit in temperatures. Even reviews by people with no stake in the frames themselves.

Yeah, it's a bit tricky to check without removing the cooler... I'm also thinking that if the frame has been shown to improve temps, then I'd rather just install it straight away. It's not that fun to take the system apart and install the frame later on.

Also saw GN's test of Thermaltake's variant of the frame. Much cheaper, seems to work as well, and I can actually find it in stock. I think I'll go with that one.

 

[IntelUser2000]

In terms of die area, 12P + 16E = 8P + 28.4E using current RPL dimensions.

The E cores are relatively smaller with Meteorlake so 1P = 4E is roughly true. Besides, they wouldn't go with the oddball configuration and go all 32E cores if they wanted it for a very small increase in die size.

Being the first generation, Alderlake is pretty much the worst as the hybrid implementation goes.

 

[Hulk]

The E cores are relatively smaller with Meteorlake so 1P = 4E is roughly true. Besides, they wouldn't go with the oddball configuration and go all 32E cores if they wanted it for a very small increase in die size.

Being the first generation, Alderlake is pretty much the worst as the hybrid implementation goes.

If the P's and E's are fabricated on the same process how have they increased the E to P ratio from the current 3.1:1 to 4:1? I assume either the P's are getting larger or the E's are getting smaller or a combination of both?

 

[A///]

So tell us, if AMD weren't caught in the dark, what would they have released?

Provide a time machine to go back 3-4 years when zen 4 development began. Intel's e core development likely began in 2014-2016. Not after zen 2 like some young people believe. Intel has smart engineers. lots of them. but even they couldn't get out a product like alderlake in under 2 years.

in regard to your 10%, intel releases a product almost every 12 months while amd's development schedule is longer. buy every other generation for intel.

 

[RTX2080]

Good question and actually that's the beauty of Intel's strategy. If you need more than 8 cores then you have an application this is very effectively multithreaded so it will do well with 16E cores or more. In fact as the bulk of applications become better multithreaded we could see the P's be reduced to 4 and the E's to 32 or 40.

The reason why Intel keep 8 P core is gaming and daily productivity usage, these usage would never being well threaded especially in latency sensitive situation. Reducing P core is a suicide decision. I think more than 16E won't happen, it would even possible to be reduced in the future, because using E core is just the reflection of process node disavantage.

 

[TheELF]

Provide a time machine to go back 3-4 years when zen 4 development began. Intel's e core development likely began in 2014-2016. Not after zen 2 like some young people believe. Intel has smart engineers. lots of them. but even they couldn't get out a product like alderlake in under 2 years.

in regard to your 10%, intel releases a product almost every 12 months while amd's development schedule is longer. buy every other generation for intel.

So we are saying the same thing, amd wasn't caught by surprise, zen4 is all amd could have released without a new node.

 

[A///]

The reason why Intel keep 8 P core is gaming and daily productivity usage, these usage would never being well threaded especially in latency sensitive situation. Reducing P core is a suicide decision. I think more than 16E won't happen, it would even possible to be reduced in the future, because using E core is just the reflection of process node disavantage.

Nothing about that leak made sense.

 

[OneEng2]

Now that we've had over a year to test and discuss Intel's hybrid approach with both Alder and Raptor Lake I think we can come to some reasonable conclusions as to why they went down this path. Here's my version of this "story."

First, we have to assume they had a pretty good idea of their performance targets Zen 2, 3, 4.. at the time these parts were on the drawing board and they also had a pretty good idea of the transistor density they could achieve. It would have been obvious to them that they were not going to be able to compete on a core-for-core basis given the node deficit without creating huge parts and impacting the financial bottom like significantly.

With a die the size of the current 8+16 Raptor Lake die they could fit about 13.1 P cores, which would score about 35,000 in Cinebench R23, MT. Good but not enough to beat Zen 4. Furthermore using all E cores they could achieve a score of over 47,000, which would win the MT Cinebench war but of course lose in so many applications requiring ST performance.

This is where I think the Intel designers got it right. They figured that most applications currently that are not highly parallel don't use more than 8 or so cores at once so they went with the hybrid approach to mitigate their node deficiency. Whether or not you like it, given their fabrication limitations it is a good solution and has kept them competitive with AMD, who have equally good big core architecture and better process.

There is no doubt that in order to be competitive they not only had to employ the hybrid approach but also do the best they could from an efficiency point of view because AMD (TSMC) had them there as well. The final piece of the puzzle is because Intel has their own fabs and a significant war chest they could also confront AMD on price. When you put all of this together you see how we've come to the point where we have to very good brand choices at a variety of price points.

The data in the attachment were recorded with max power PL1 and PL2 set at 175W, which I think is reasonable, especially on air cooling. You can see that the E's do quite a bit for efficiency in terms of both area for the compute they generate as well as compute for the power they consume.

I mostly agree.

In the desktop, Intel did a great job of obtaining parity and even eclipsing Zen 4 performance in many cases by the use of "Big/Little" and by throwing power budget out the window. These trade-offs make sense in the desktop.

In the laptop market, my feeling is that Zen 4 and RDNA2 on TSMC N5 will be a much more trouble to Intel's Raptor Lake design (time will tell). Considering the market makeup of laptop vs desktop, this will likely be the more important battle between the 2 companies.

In the server market, AMD's design and scaling appear to dominate anything that Intel can put on the table throughout 2023. I suspect AMD would be perfectly willing to sacrifice market share in the PC Desktop to Intel in exchange for even more server market share.

For me, this comes down to Intel being able to meet its process roadmap. On paper, Intel is poised to dominate transistor density by 2024. My personal engineering opinion is that Intel's process roadmap is dangerously optimistic. Every process step involves big changes and advancements. Every process step is scheduled to coincide with a new CPU architecture. While this looks good on paper, will Intel be able to pull this off? Intel's transition to 10nm was a disaster. They are in the process of laying off a ton of engineers. To me, it seems like an impossibly difficult task that Intel executives are asking of Engineering. It took Intel 10 years to dig the hole they are in. I find it very hard to see a way for them to climb out of it in 3.

FWIW, I could easily be wrong. When Intel nose dived with Itanium and P4 I didn't see the Israel team bailing the company out with Conroe either . Of course, Intel still had the process advantage then.

from here:

https://www.granitefirm.com/blog/us/2021/12/28/tsmc-process-roadmap/

AMD vs Intel CPU Roadmap 2024-2025: Ryzen AI vs Core Ultra | Hardware Times

Intel plans to launch Arrow/Lunar Lake later this year, while AMD will roll out the Ryzen 9000 and Epyc Turin CPUs this fall.

www.hardwaretimes.com

 

[Hulk]

There is a continuum between single threaded applications and multithreaded applications. Today, most applications will utilize more than one thread. More so than 5 years ago. 5 years in the future even more applications will be better multithreaded. If all applications were like Cinebench, or nearly 100% multithreaded we would have no use for the P cores at all and the most efficient, performant, and cost effective CPU would consist of a swarm of E cores.

We are in transition to better multithreading usage in applications. Intel picked 8 as the magic number when they hatched this plan probably 5 or 6 years ago. That was actually pretty forward thinking of them.

Looking ahead they could be thinking that 6 P's may be enough and the remaining resources should be spent on increasing the IPC of the E's.

Like it or not, as far as the hybrid approach goes on the desktop TSW!

 

[igor_kavinski]

Like it or not, as far as the hybrid approach goes on the desktop TSW!

How do you find your regular workflow with the 13900K? All complaints regarding E-core performance gone?

 

[Hulk]

I mostly agree.

In the desktop, Intel did a great job of obtaining parity and even eclipsing Zen 4 performance in many cases by the use of "Big/Little" and by throwing power budget out the window. These trade-offs make sense in the desktop.

In the laptop market, my feeling is that Zen 4 and RDNA2 on TSMC N5 will be a much more trouble to Intel's Raptor Lake design (time will tell). Considering the market makeup of laptop vs desktop, this will likely be the more important battle between the 2 companies.

In the server market, AMD's design and scaling appear to dominate anything that Intel can put on the table throughout 2023. I suspect AMD would be perfectly willing to sacrifice market share in the PC Desktop to Intel in exchange for even more server market share.

For me, this comes down to Intel being able to meet its process roadmap. On paper, Intel is poised to dominate transistor density by 2024. My personal engineering opinion is that Intel's process roadmap is dangerously optimistic. Every process step involves big changes and advancements. Every process step is scheduled to coincide with a new CPU architecture. While this looks good on paper, will Intel be able to pull this off? Intel's transition to 10nm was a disaster. They are in the process of laying off a ton of engineers. To me, it seems like an impossibly difficult task that Intel executives are asking of Engineering. It took Intel 10 years to dig the hole they are in. I find it very hard to see a way for them to climb out of it in 3.

FWIW, I could easily be wrong. When Intel nose dived with Itanium and P4 I didn't see the Israel team bailing the company out with Conroe either . Of course, Intel still had the process advantage then.

from here:

https://www.granitefirm.com/blog/us/2021/12/28/tsmc-process-roadmap/

AMD vs Intel CPU Roadmap 2024-2025: Ryzen AI vs Core Ultra | Hardware Times

Intel plans to launch Arrow/Lunar Lake later this year, while AMD will roll out the Ryzen 9000 and Epyc Turin CPUs this fall.

www.hardwaretimes.com

I agree completely. If you remember the move from 22nm to 14nm was even semi-disaster for Intel and I think one of the reasons why Broadwell was really just a mobile release.

10 years ago I would never have suspected Intel would not have a significant process advantage. Now, like you, I don't have faith they can execute on their node plan. We shall see.

As for mobile I find it strange that there are so few reviews of Alder Lake U parts. It's really hard to find benchmarks and even harder to find head-to-head comparisons of Intel vs. AMD current mobile parts.

 

[jpiniero]

As for mobile I find it strange that there are so few reviews of Alder Lake U parts. It's really hard to find benchmarks and even harder to find head-to-head comparisons of Intel vs. AMD current mobile parts.

Notebookcheck has a bunch. Here's one with the "9 W" 1250U (with a PL1 of 23 W):

https://www.notebookcheck.net/2022-HP-Envy-x360-13-convertible-review-Core-i5-1230U-or-Core-i7-1250U.662349.0.html

 

[Hulk]

How do you find your regular workflow with the 13900K? All complaints regarding E-core performance gone?

I love the 13900K. It's a beast. I have it set at 175W and on lightly threaded workloads 2 P's will ramp up to 5.8GHz. It's also great for multitasking. For example, I'll be frameserving a Vegas Pro timeline to Handbrake for rendering using those 16E's while doing Photoshop work with the P's in the foreground. If I do a compute heavy task like perspective correction I'll hear the CPU fan ramp up for like 2 seconds and then shut down. All the while my editing experience is seamless and by that I mean real time, I'm not waiting on the computer, which makes for a more creative and fun edit.

As for "TSW." I have an old pair of AR TSW610 from college. I still love them. The joke from one of the engineers supposedly was that TSW stood for "This Sh*t Works!" In reality the advertising said TitaniumSolidWood, which makes more sense of course.

Anyway with 16E's available TSW!

 

[Hulk]

I have to say for the PC enthusiast the hours of testing alone is worth the price of admission for my 13900K. I've finally managed to "corner" those E's! Don't know why I didn't think of this before.

Here's the setup. 1+16 with the E's running 4.3 and the P running 1.4GHz, it's basically doing nothing and consuming about 2W.

First fun fact. At 4.3GHz an E core uses about 7.5 Watts. I'm fairly confident about that number.

Second. Running CPUmark99 the Thread Director correctly runs it on an E core as the result is 727, which is solidly in Skylake range. A P at 1.4 would give a much lower result. Also, per GHz Gracemont has better IPC in CPUmark99 than Golden Cove or Raptor Cove.

Third. Cinebench ST for an E at 4.3 is 1171. Finally a number I can believe. Again, solidly in Skylake territory.

Finally the Handbrake test comes in at 224 seconds. Given that the one P core at 1.4GHz isn't doing much these 16E's at 4.3 GHz are faster than a 11900K (219 seconds), 10900K (234 seconds), and 5800X (240 seconds). My old 4770K ran this test in 813 seconds. So the E cores in the 13900K are like tacking on 3.5 4770K's to the Golden Coves.

 

[Henry swagger]

https://twitter.com/x/status/1589240603250151424

Beautiful raptor lake shots

 

[nicalandia]

If the P's and E's are fabricated on the same process how have they increased the E to P ratio from the current 3.1:1 to 4:1? I assume either the P's are getting larger or the E's are getting smaller or a combination of both?

Different part of the core scale differently since The P core and E cores have different design they will scale differently, but nothing as drastic as you believe, The Golden Cove to Gracemont Core ratio is still about 4:1(7.123 mm^2 vs 1.5 mm^2 so technically 4.5:1), but those little e cores are not all by themselves are they right?

They are in a Cluster(Quad Core Cluster to be precise), the cluster size is 8.296 mm^2 wich is 16% larger than a single Golden Cove.

Now to the Meteor Lake side: Redwood Cove size is 5.33 mm^2 and The Crestmont core size is 1.046 mm^2 which is 5:1, but as mentioned before those little e cores come in clusters, so for MTL the cluster size is 5.907 which is 11%


I would like to point out that the only source we have on Redwood Cove/Crestmont comes from a mobile die which is likely MTL-H, which restricts Crestmont cores to 3MiB of L2, I suspect that MTL-S Crestomont cores to have either 6MiB of L2 per Cluster(or at the very least 4MiB), that will increase the cluster size past 6 mm^2 bringing the ration back to what we currently are with Raptor Cove/Raptormont



Source: https://semianalysis.substack.com/p/meteor-lake-die-shot-and-architecture