Because non-cringe MFMA implementation is only possible with SoIC. Mainly though it is provocative, it gets the people going.
Flagship dGPU gets to access super fast GDDR7 up to 512bit. Medusa Halo will probably go with 192 or 384bit LPDDR6.
I think Medusa Halo will be 384-bit LPDDR5X using 2 LPCAMM modules optimally.
LPDDR6 will be pretty scarce and expensive.
For the dGPU, GDDR7 will be faster, more available and cheaper to a degree than today so you could just keep it simple with a mono N3P part.
But there is a size where the optimal perf/cost crossover is a smaller GDDR7 bus with a fat MALL stacked below the compute.
Or you could have both a fat bus and fat cache, though a 512b stacked part would need insane compute to justify such bandwidth.
Then again NV went all out on GB202 bandwidth and yeah, kinda doesn't have the compute to justify it.
3GB dies will also be quite common by then, that can be a big consideration moreso on smaller die configs.
Unless by flagship you mean the Instinct line.
Instinct spares no expense for absolute performance. It uses the best tech available at the time it is made without throwing yields out the window.
So yeah, MI400 and Venice Dense are gonna hold back nothing.