Discussion RDNA 5 / UDNA speculation

[adroc_thurston]

Multiple multimedia engines for AI input/output I'm guessing?

No, configurable I/O.
MI300 already has like 12 media cores.

Presumably it will all be hooked up like N4C would've been.

Duh.
Gotta ramp the D2D bandwidth and all.

 

[stayfrosty]

Isn't a design with only 2 retscale AID's kind of small? I thought with CoWoS going 5.5x reticle they would scale bigger. The design doesn't seem that much larger than the MI355x (which also has 2x retscale AID's)

 

[Win2012R2]

Isn't a design with only 2 retscale AID's kind of small?

A lot easier (and cheaper) if you have only 2 diff AIDs.

 

[basix]

If you extract things like media engines, Infinity Fabric IO/PHY, PCIe and reduce the amount of chip-to-chip interfaces you get much more usable Die area. At the same time, energy efficiency gets improved. Especially if you compare it to a 6x Base Die configuration (Die-to-Die interconnects, increased bandwidth requirements, pJ/bit). And I don't know if AMD sticks to CoWoS or changes back to EFB like used on MI250X.

The current Base Die is 13 x 29mm according to AMD. If you go beyond 800mm2 and exctract before mentioned IP-Blocks, you might land at 1.3x more usable area. Combined with N4 instead of N6 and 6um SoIC instead of 9um SoIC the gains are quite decent.
The same applies to the Top Die. You can now increase its Die Size by 1.3x (more stuff can be kept on same chip) and N3 greatly increases transistor density.

Another benefit: You do not need two Base Die version (normal and mirrored).

If you go forward to MI400 you could extend that to 12x HBM stacks and possible 3x Base Die, I don't know. But increased usable Die area and no need for Base Die mirroring stays as benefits. It would then somehow look like Clearwater Forest from Intel. But with HBM4 and much bigger Die as additions.

And maybe as an extra:
You could more easily switch or extend your Infinity Fabric Phy with e.g. LPDDR5/6 PHY and add much more and cheaper memory capacity

 

[stayfrosty]

If you go forward to MI400 you could extend that to 12x HBM stacks and possible 3x Base Die, I don't know. But increased usable Die area and no need for Base Die mirroring stays as benefits. It would then somehow look like Clearwater Forest from Intel. But with HBM4 and much bigger Die as additions.

Agree with all you said and it absolutely makes sense for MI355x. But i'm just a bit disappointed that apparently according to the article linked in the previous page that MI400 will stay with a 2x Base Die setup. So in absolute terms the design will not be THAT much bigger than MI355x. Well, except if they start stacking compute chiplets, but I doubt that.

 

[Kepler_L2]

Combined with N4 instead of N6 and 6um SoIC instead of 9um SoIC the gains are quite decent.

MI400 AID/MID are N3P

 

[stayfrosty]

MI400 AID/MID are N3P

That's hella expensive for some PHY's and Cache. I'm guessing the compute chiplets will be N2(P) and bonded with 4.5um SoIC then?

 

[Kepler_L2]

That's hella expensive for some PHY's and Cache. I'm guessing the compute chiplets will be N2(P) and bonded with 4.5um SoIC then?

For the XCD I don't know the node, but some N2 variant is likely imo.

 

[basix]

MI400 AID/MID are N3P

Interesting.

Even more space for "stuff"

Agree with all you said and it absolutely makes sense for MI355x. But i'm just a bit disappointed that apparently according to the article linked in the previous page that MI400 will stay with a 2x Base Die setup. So in absolute terms the design will not be THAT much bigger than MI355x. Well, except if they start stacking compute chiplets, but I doubt that.

Still, if N3P for AID and MID is true, ~800mm2 AID and let's say ~200...250mm2 for each MID ist ist still much more area than MI300X and also Blackwell. And then add the fact, that compared to Blackwell you add another +600mm2 or so N2 XCDs on each AID. This thing is HUGE.

Additionally, you can scale that design to 3x AIDs, 12x XCDs and 12x HBM-Stacks. Maybe as an MI400 refresh one year later?