Discussion RDNA4 + CDNA3 Architectures Thread

[DisEnchantment]

With the GFX940 patches in full swing since first week of March, it is looking like MI300 is not far in the distant future!
Usually AMD takes around 3Qs to get the support in LLVM and amdgpu. Lately, since RDNA2 the window they push to add support for new devices is much reduced to prevent leaks.
But looking at the flurry of code in LLVM, it is a lot of commits. Maybe because US Govt is starting to prepare the SW environment for El Capitan (Maybe to avoid slow bring up situation like Frontier for example)

See here for the GFX940 specific commits

History for llvm/lib/Target/AMDGPU - llvm/llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. - History for llvm/lib/Target/AMDGPU - llvm/llvm-project

github.com

Or Phoronix

More AMD "GFX940" Enablement Work Landing In LLVM - Phoronix

www.phoronix.com

There is a lot more if you know whom to follow in LLVM review chains (before getting merged to github), but I am not going to link AMD employees.

I am starting to think MI300 will launch around the same time like Hopper probably only a couple of months later!
Although I believe Hopper had problems not having a host CPU capable of doing PCIe 5 in the very near future therefore it might have gotten pushed back a bit until SPR and Genoa arrives later in 2022.
If PVC slips again I believe MI300 could launch before it

This is nuts, MI100/200/300 cadence is impressive.



Previous thread on CDNA2 and RDNA3 here

Question - Speculation: RDNA3 + CDNA2 Architectures Thread

Man I have been dying to make this one for a while now. First rumours for RDNA3 are here so new thread time! Just going to start off with this one for now: kopite7kimi on Twitter: "@VideoCardz Ah, I mean a simple mcm design with 10240 cores is not enough. Because the lift from RDNA2 to RDNA3...

forums.anandtech.com

 

[Joe NYC]

Well no, lambdadelta-kun knows his stuff.

Interesting. most people believe that only monolithic RDNA4 dies survived.

 

[Joe NYC]

That's still N4c.

Well, it was 1 to 3 SEDs per IO die, 9 total. Which was just a waste / going overboard with potential segmentation of using less than 3 per IO die. Those 3 tiny SED could have been one bigger die.

What I was thinking was a single SED that 3 times the size. But then, instead of 1 (bigger) SED on top of 1 IO die and then connecting 1 to 3 IO dies, I was suggesting a monolithic IO die - 3 different sizes of them. Then, there would be no jumping between IO dies, no need for 3D silicon bridges or 2.5D connections of IO dies. Only 3D jumps from IOD to SED.

 

[adroc_thurston]

Well, it was 1 to 3 SEDs per IO die, 9 total

That's an IOD.
IOC was a separate thing.

Those 3 tiny SED could have been one bigger die.

You're SoIC bonding stuff, keep em SE-sized.
It's in the name.

I was suggesting a monolithic IO die - 3 different sizes of them.

That limits the amount of Si you spam. No bueno.

 

[Ajay]

Well no, lambdadelta-kun knows his stuff.

Well then, this is going to be very interesting.

 

[adroc_thurston]

Well then, this is going to be very interesting.

Yeah he got someone inside AMD Shanghai or he works there altogether.
Knows very specific stuff far in advance.

 

[eek2121]

That's still N4c.

I think a bunch of people are going to be shocked when next gen launches.

(which is NOT at Computex unless AMD is pulling another one with certain "partners")

 

[adroc_thurston]

I think a bunch of people are going to be shocked when next gen launches.

no.

(which is NOT at Computex unless AMD is pulling another one with certain "partners")

They're still gonna talk about it there.

 

[Joe NYC]

That's an IOD.
IOC was a separate thing.

I think they call it AID = Active Interposer Die
in Mi300 and Navi4c

You're SoIC bonding stuff, keep em SE-sized.

I don't know how they automate this stuff if it is not cheaper to bond one bigger piece of silicon rather than 3 small ones.

I am not sure if graduality for creating SKUs would be worth it.

It's in the name.

That limits the amount of Si you spam. No bueno.

Well, that's the big downside, of a tradeoff. More modularity at expense of having 2.5D or silicon bridges vs. less modularity, more SI spam

 

[adroc_thurston]

I think they call it AID = Active Interposer Die
in Mi300 and Navi4c

yea.

I don't know how they automate this stuff if it is not cheaper to bond one bigger piece of silicon rather than 3 small ones.

The # of KGDs matters a lot less than the actual bonding process being kinda slow.

 

[eek2121]

no.

🤣

You know they will! Can you guess when it launches because I know. 🤣

🤣

 

[adroc_thurston]

🤣

🤣

?

 

[Joe NYC]

yea.

The # of KGDs matters a lot less than the actual bonding process being kinda slow.

Maybe the old sweet spot for die size (vs. # of bonds) was in 100mm2 range, but it seems that maybe that sweet spot is higher. Assuming the rumors of bigger die sizes in Mi400 are bigger.

That would have some implications on chiplet based RDNA 5.

 

[adroc_thurston]

Assuming the rumors of bigger die sizes in Mi400 are bigger.

MI400 bigger XCD has more to do with L2 coherency tracking than any yielded die area concerns.

 

[branch_suggestion]

https://twitter.com/x/status/1795278962110963968

Jebaited™

 

[adroc_thurston]

https://twitter.com/x/status/1795278962110963968

Jebaited™

Fits his profile pic alright.

 

[branch_suggestion]

Fits his profile pic alright.

I do say, trusting a Umineko poster on face value never ends well.
Unless it's Battler.

 

[Mahboi]

ac,radeonsi: add more gfx11 APUs, gfx12 fixes, update addrlib (!29313) · Merge requests · Mesa / mesa · GitLab

Mesa 3D graphics library

gitlab.freedesktop.org

Mesa firing some GFX1150 and GFX12 patches.

Edit: https://gitlab.freedesktop.org/mesa...t_id=34be14d957aa6e4252a9d61b5d5ad7cb74a8424d
"Use compute if the size is large enough. Always prefer compute on GFX12."

?

 

[jpiniero]

?
You just have an edge filled with USRs and the other edge has serial I/O.
Simple as.

By "IO" I was including things like display engines and media encoders.

 

[Tuna-Fish]

https://gitlab.freedesktop.org/mesa...t_id=34be14d957aa6e4252a9d61b5d5ad7cb74a8424d
"Use compute if the size is large enough. Always prefer compute on GFX12."

?

The function is used to clear a buffer (set it to all 0) starting from the CPU side. There are two methods, use DMA memory accesses to write zeroes to the buffer, or to launch a compute function on the GPU side to clear it from that side. For large buffer sizes, the compute method was always faster. For small sizes, there used to be a bunch of logic to pick which method to use, presumably because the overhead of dispatching a compute task was too high for it to be worth it. For GFX12, it just always uses the GPU compute task.

Also presumably, this means that the overhead of launching compute tasks has been reduced.

 

[Mahboi]

Beautiful.
Compute first world here we come.

 

[soresu]

Beautiful.
Compute first world here we come.

From the design of UE5 Lumen and Nanite it sounds like we're already well on the way there.

 

[Mahboi]

From the sound of the design of UE5 Lumen and Nanite it sounds like we're already well on the way there.

I'd consider mesh/primitive shaders as the real first step forward.
When I heard about it I was pretty floored to learn that the entire SW stack in GPUs was "gaming first" and didn't properly decouple compute from gaming since the 90s.
We're clearing up legacy logic in this industry, feels nice.

 

[soresu]

I'd consider mesh/primitive shaders as the real first step forward.

Oh for sure, I was meaning on the software side of actually putting it to use.

That being said primitive shaders definitely came first, albeit b0rked along with the NGC (New Geometry Compute?) part of the 1st gen Vega hardware.

 

[soresu]

I think primitive shaders were part of one of the mid season console refresh GPUs, I'd be interested to know if it worked on that at least.

 

[blackangus]

I'd consider mesh/primitive shaders as the real first step forward.
When I heard about it I was pretty floored to learn that the entire SW stack in GPUs was "gaming first" and didn't properly decouple compute from gaming since the 90s.
We're clearing up legacy logic in this industry, feels nice.

This is an interesting statement to me. I don't do any development on GPU's, and software is my second priority, so can you expand on this statement to help me understand a bit more of what is improving and how that will help game development? (Will it?)