Discussion RDNA4 + CDNA3 Architectures Thread

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DisEnchantment

Golden Member
Mar 3, 2017
1,754
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With the GFX940 patches in full swing since first week of March, it is looking like MI300 is not far in the distant future!
Usually AMD takes around 3Qs to get the support in LLVM and amdgpu. Lately, since RDNA2 the window they push to add support for new devices is much reduced to prevent leaks.
But looking at the flurry of code in LLVM, it is a lot of commits. Maybe because US Govt is starting to prepare the SW environment for El Capitan (Maybe to avoid slow bring up situation like Frontier for example)

See here for the GFX940 specific commits
Or Phoronix

There is a lot more if you know whom to follow in LLVM review chains (before getting merged to github), but I am not going to link AMD employees.

I am starting to think MI300 will launch around the same time like Hopper probably only a couple of months later!
Although I believe Hopper had problems not having a host CPU capable of doing PCIe 5 in the very near future therefore it might have gotten pushed back a bit until SPR and Genoa arrives later in 2022.
If PVC slips again I believe MI300 could launch before it

This is nuts, MI100/200/300 cadence is impressive.



Previous thread on CDNA2 and RDNA3 here

 
Last edited:

gaav87

Senior member
Apr 27, 2024
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794
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Does 16x32 mean doubled INT4 rate for RDNA4 compared to RDNA3?

For the V_SWMMAC_I32_16X16X64_IU4 (rdna4 swmma)
INT4
A: 16×16 stored/32×16 actual
B: 16×64
Result: 32×64 INT32

For the V_WMMA_I32_16X16X32_IU4: (rdna4 new wmma)
A: 16×16 INT4
B: 16×32 INT4
Result: 16×32 INT32

For the V_WMMA_I32_16X16X16_IU4: (rdna3 wmma)
iNT4
Result: 16x16 INT32

Dimension:
16×16 INT32 matrix: 256 elem × 4 bytes= 1 KB
32×64 INT32 matrix: 2048 elem × 4 bytes= 8 KB
So rdna4 swmma int32 matrix is 8 time larger than rdna3
and wmma 2x as big as 16x16
 

gaav87

Senior member
Apr 27, 2024
452
794
96
Does 16x32 mean doubled INT4 rate for RDNA4 compared to RDNA3?
So yes the 16×32 INT4 = higher rate of computation compared to 16×16 INT4 theorethicaly 16×32 INT4 operation can process 2x as many elements in parallel vs rdna3. ofc if the mem bandwidth and processing are not bottlenecking.
 

Gideon

Golden Member
Nov 27, 2007
1,921
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AMD released some dibits of info:



  • Optimized Compute Units
  • Enhanced AI Compute capabilities (2nd-generation AI accelerators)
  • Improved Raytracing performance per Compute Unit (3rd-generation Raytracing accelerators)
  • Better media encoding quality (2nd-generation AMD Radiance Display Engine)
  • 4nm manufacturing process

But no performance slides. I guess the GPUs are still quite a while away, or the comparison is not that flattering to RDNA4. Might also just wait for Nvidia to make the next move. Either way this probably means we still have to wait quite a bit until we get more info
 

coercitiv

Diamond Member
Jan 24, 2014
6,956
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But no performance slides. I guess the GPUs are still quite a while away, or the comparison is not that flattering to RDNA4. Might also just wait for Nvidia to make the next move. Either way this probably means we still have to wait quite a bit until we get more info
It's almost like they need permission from Nvidia to speak. First they have to wait and see what Nvidia does, then they come out barking at the fence for 15 minutes during a keynote. Rinse and repeat in 2 years.
 

adroc_thurston

Diamond Member
Jul 2, 2023
4,714
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It's almost like they need permission from Nvidia to speak. First they have to wait and see what Nvidia does, then they come out barking at the fence for 15 minutes during a keynote. Rinse and repeat in 2 years.
No halo means you can't talk. Simple as.
They can't command the pricing stack without a 3kilobick tiled monstrosity. Which they killed.
 
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