Discussion RDNA4 + CDNA3 Architectures Thread

[DisEnchantment]

With the GFX940 patches in full swing since first week of March, it is looking like MI300 is not far in the distant future!
Usually AMD takes around 3Qs to get the support in LLVM and amdgpu. Lately, since RDNA2 the window they push to add support for new devices is much reduced to prevent leaks.
But looking at the flurry of code in LLVM, it is a lot of commits. Maybe because US Govt is starting to prepare the SW environment for El Capitan (Maybe to avoid slow bring up situation like Frontier for example)

See here for the GFX940 specific commits

History for llvm/lib/Target/AMDGPU - llvm/llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. - History for llvm/lib/Target/AMDGPU - llvm/llvm-project

github.com

Or Phoronix

More AMD "GFX940" Enablement Work Landing In LLVM - Phoronix

www.phoronix.com

There is a lot more if you know whom to follow in LLVM review chains (before getting merged to github), but I am not going to link AMD employees.

I am starting to think MI300 will launch around the same time like Hopper probably only a couple of months later!
Although I believe Hopper had problems not having a host CPU capable of doing PCIe 5 in the very near future therefore it might have gotten pushed back a bit until SPR and Genoa arrives later in 2022.
If PVC slips again I believe MI300 could launch before it

This is nuts, MI100/200/300 cadence is impressive.



Previous thread on CDNA2 and RDNA3 here

Question - Speculation: RDNA3 + CDNA2 Architectures Thread

Man I have been dying to make this one for a while now. First rumours for RDNA3 are here so new thread time! Just going to start off with this one for now: kopite7kimi on Twitter: "@VideoCardz Ah, I mean a simple mcm design with 10240 cores is not enough. Because the lift from RDNA2 to RDNA3...

forums.anandtech.com

 

[In2Photos]

Why would AMD waste this opportunity, though?

The only way they can get a meaningful advantage out of a 32GB card is if it's significantly cheaper than the 5090.

The idea here is to have a card sit above the 9070 XT that they can ask 300-500$ more for even though it's barely faster and only like 50$ more expensive to make, but takes away "local AI LLM that fit into 32GB" desktop marketshare from the 5090.

It doesn't matter how much vRAM it has, if it isn't faster than the 5090 it isn't going to take away from the 5090 market share. Nor the 5080 for that matter. At least not in any way that's meaningful.

 

[gaav87]

96 ROP ?

 

[Shmee]

96 ROP ?

View attachment 117033

View attachment 117034

Wow why is it so many Euros? I thought this was gonna be under $600...

 

[Kepler_L2]

Yeah i think there 96 rops and PxF is higher, just GPU Z need update

128, it's 4 SEs

 

[gaav87]

Im stopping the search coz i got depressed.

 

[gaav87]

260W for reaper ?

 

[gdansk]

128, it's 4 SEs

Is frontend clock rate still separate from shaders?

 

[Kepler_L2]

Is frontend clock rate still separate from shaders?

Dunno

 

[Win2012R2]

Dunno

Was it even better to have separate clocks or the jury is still out on this one?

 

[Kepler_L2]

Was it even better to have separate clocks or the jury is still out on this one?

It's a requirement when going chiplets pretty much.

 

[Win2012R2]

It's a requirement when going chiplets pretty much.

Would not having same clock be better though for sync?

When RDNA3 had it I thought it was desperate measure to make t**d look better than it is

 

[reaperrr3]

When RDNA3 had it I thought it was desperate measure to make t**d look better than it is

You have to design these things into the chip/uArch long before even knowing whether a chip is going to be worse than planned, and usually you wouldn't waste resources on implementing a hardware feature if it's just an emergency marketing backup plan with no real benefit.

 

[Win2012R2]

it's just an emergency marketing backup plan with no real benefit.

Seemed that way to me during RDNA3 launch - it diff clock was planned then it would not be like 10% different, it's way too small, way too desperate

 

[itsmydamnation]

Seemed that way to me during RDNA3 launch - it diff clock was planned then it would not be like 10% different, it's way too small, way too desperate

That's such a dumb take, 10% is like double the power when at the high end of the clock/ voltage curve.

 

[Win2012R2]

10% is like double the power when at the high end of the clock/ voltage curve.

Desperate or dumb then?

 

[coercitiv]

Desperate or dumb then?

I think the point was that 10% at high end of clock/voltage curve is quite a lot.

 

[itsmydamnation]

Desperate or dumb then?

Or balanced and optimised

 

[Win2012R2]

I think the point was that 10% at high end of clock/voltage curve is quite a lot.

Sure, my point was that it seems to me having desynced clocks was bringing in marginal benefits at best (at 10% ain't going to do loads) and it looks more desperate than planned - or perhaps more likely the other clock did not hit target level, which is why desyncing happened.

 

[reaperrr3]

Sure, my point was that it seems to me having desynced clocks was bringing in marginal benefits at best (at 10% ain't going to do loads) and it looks more desperate than planned - or perhaps more likely the other clock did not hit target level, which is why desyncing happened.

Well, my point was you can't desync clocks like that unless you put the frontend into its own clock domain during the chip/uarch design phase, in other words at a time when they were still thinking RDNA3 would do much better than it ended up doing.
Which they wouldn't do if there was no benefit to it, as an extra clock domain isn't free in terms of area or design cost.

 

[Win2012R2]

in other words at a time when they were still thinking RDNA3 would do much better than it ended up doing.

Is it even sensible to have separate clock domain when the difference in clocks is expected to be fairly low, is it mainly to save power on idle rather than perf thing?

 

[Timorous]

Is it even sensible to have separate clock domain when the difference in clocks is expected to be fairly low, is it mainly to save power on idle rather than perf thing?

How do we know at design time the difference in clocks was meant to be low? If RDNA 3 was designed to be very high speed then it stands to reason the expected delta between the domains was greater than it ended up being.

 

[SolidQ]

900W???

 

[Timorous]

900W???

Think they need to account for the people who will pair it with a 14900KS...

 

[Win2012R2]

How do we know at design time the difference in clocks was meant to be low?

They clearly missed the main clock target, but they could not have missed it by THAT much and we know the difference on release is low.

 

[Timorous]

They clearly missed the main clock target, but they could not have missed it by THAT much and we know the difference on release is low.

We don't know what the clock target was. We do have this slide though

And the actual clocks seem to have missed by quite a lot on N31.