Discussion RDNA4 + CDNA3 Architectures Thread

[DisEnchantment]

With the GFX940 patches in full swing since first week of March, it is looking like MI300 is not far in the distant future!
Usually AMD takes around 3Qs to get the support in LLVM and amdgpu. Lately, since RDNA2 the window they push to add support for new devices is much reduced to prevent leaks.
But looking at the flurry of code in LLVM, it is a lot of commits. Maybe because US Govt is starting to prepare the SW environment for El Capitan (Maybe to avoid slow bring up situation like Frontier for example)

See here for the GFX940 specific commits

History for llvm/lib/Target/AMDGPU - llvm/llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. - History for llvm/lib/Target/AMDGPU - llvm/llvm-project

github.com

Or Phoronix

More AMD "GFX940" Enablement Work Landing In LLVM - Phoronix

www.phoronix.com

There is a lot more if you know whom to follow in LLVM review chains (before getting merged to github), but I am not going to link AMD employees.

I am starting to think MI300 will launch around the same time like Hopper probably only a couple of months later!
Although I believe Hopper had problems not having a host CPU capable of doing PCIe 5 in the very near future therefore it might have gotten pushed back a bit until SPR and Genoa arrives later in 2022.
If PVC slips again I believe MI300 could launch before it

This is nuts, MI100/200/300 cadence is impressive.



Previous thread on CDNA2 and RDNA3 here

Question - Speculation: RDNA3 + CDNA2 Architectures Thread

Man I have been dying to make this one for a while now. First rumours for RDNA3 are here so new thread time! Just going to start off with this one for now: kopite7kimi on Twitter: "@VideoCardz Ah, I mean a simple mcm design with 10240 cores is not enough. Because the lift from RDNA2 to RDNA3...

forums.anandtech.com

 

[HurleyBird]

Packaging is the easy part.

What's the hard part then?

 

[PJVol]

What's the hard part then?

two most likely and known issues, with architecture (early design step flaw) and with process tech (revealed at tape-out )?

 

[adroc_thurston]

What's the hard part then?

Making it work correctly with graphics APIs.

with architecture (early design step flaw) and with process tech (revealed at tape-out )?

Neither are anything out of ordinary there.

 

[GodisanAtheist]

Making it work correctly with graphics APIs.

-But that shouldn't come as a surprise to AMD. DX 11/12 has been out for a good long while now, why make a whole arch around APIs that don't like chiplets?

Seems silly, AMD certainly wouldn't have expected the arch to magically work, they would have certainly put a lot of effort into the software side first. Right? Right?!

 

[adroc_thurston]

why make a whole arch around APIs that don't like chiplets?

Because they gotta build big and take heads, simple as.

Seems silly, AMD certainly wouldn't have expected the arch to magically work, they would have certainly put a lot of effort into the software side first. Right? Right?!

It's all about schedules and not whatever you imagined.
They gotta ship and if they ship too late the product becomes pointless.

 

[GodisanAtheist]

Because they gotta build big and take heads, simple as.

-They didn't even build big with RDNA3... So much room for a 400-500mm2 GCD...

Then they suddenly decided to shoot for the moon with RDNA4?

 

[adroc_thurston]

They didn't even build big with RDNA3... So much room for a 400-500mm2 GCD...

The expectation was NV building something cheaper than AD102.
Alas!

Then they suddenly decided to shoot for the moon with RDNA4?

NV threw their cost structure out and so AMD's turn was next.

 

[Tigerick]

?Non-JEDEC GDDR7 doesn't exist.
It's a JEDEC standard.

what

new product, replaces old product.
truly bold move

Man, where is the JEDEC standard that you are referring to?

 

[adroc_thurston]

Man, where is the JEDEC standard that you are referring to?

Pay for the membership like I do and learn.

 

[Tigerick]

Pay for the membership like I do and learn.

Then I will wait for final copy of GDDR7 standard that is available for public viewing.

 

[branch_suggestion]

N21 was launched in Q4 2020 and 7800XT was launched in Q3 2023, exactly three years later. Thanks for confirming my theory

N21 worked as intended, N32, like the rest of RDNA3 has not. Part of simplifying the RDNA4 launch is to obsolete RDNA3 parts ASAP and thus the respective Ada parts, as NV has delayed client Blackwell for a myriad of reasons to 2025. Mind you the reliance of GDDR7 for RDNA4 to hit design goals without a lack of memory bandwidth and capacity does restrict how soon RDNA3 will be out of production. Reducing die size through less PHYs is worth the hassle.

and everything to do with not having monolithic backup plans in place for those segments.

Top part would be near reticle limit for a mono part.
Completely unacceptable for client, and in server MI210 is the last near reticle limit mono part AMD will ever make.

-They didn't even build big with RDNA3... So much room for a 400-500mm2 GCD...

Then they suddenly decided to shoot for the moon with RDNA4?

600mm^2 on N5 class was considered a bit outlandish due to cost, but NV did it anyway to see off even a well executed N31. Or more accurately to hit their 2x compute perf per gen increase. I guess AMD was expecting a GP102 size die.

The new schedule means NV will be without an RDNA5 competitor until late Q4 2026 at best, whilst AMD has been able to move resources to RDNA5 nice and early for a H1 2026 release. Unlike the Terascale 2 days, AMD will actually make a big die gen after their mid die gen, and win. NV could react timely, but they won't due to DC being the overwhelming R&D focus and money pit. Or maybe they still will because JHH has endless ego.
Oh, and RDNA5 is the 10th gen console IP baseline, so MS/Sony will pour resources into it, RDNA3.5/4 has some Sony resources for the PS5 Pro.

 

[moinmoin]

-But that shouldn't come as a surprise to AMD. DX 11/12 has been out for a good long while now, why make a whole arch around APIs that don't like chiplets?

Seems silly, AMD certainly wouldn't have expected the arch to magically work, they would have certainly put a lot of effort into the software side first. Right? Right?!

With the long lead times from initiating, designing and releasing new chips the changes in graphics APIs and their adoption in games while slow actually can happen faster than actually new chips getting launched. So it's not unfathomable that AMD originally bet on graphics APIs having progressed significantly more by now, and that having turned out to be a wrong prediction, N41 and N42 thus having been designed for a reality that never came to be.

AMD putting more effort into the software side is something I definitely expect them to do. But that too takes time.

 

[jpiniero]

Mind you the reliance of GDDR7 for RDNA4

I'm skeptical that they are using GDDR7 for cost reasons, even if available. 3 GB chips would be tempting though.

 

[GodisanAtheist]

With the long lead times from initiating, designing and releasing new chips the changes in graphics APIs and their adoption in games while slow actually can happen faster than actually new chips getting launched. So it's not unfathomable that AMD originally bet on graphics APIs having progressed significantly more by now, and that having turned out to be a wrong prediction, N41 and N42 thus having been designed for a reality that never came to be.

AMD putting more effort into the software side is something I definitely expect them to do. But that too takes time.

-I mean, it's not a thing AMD bets on, as one of the primary DGPU manufacturers and MS/Sony's console partner they are actively involved in making sure the next API will play nice with their hardware (so is Nvidia as the 800lb gorilla, of course).

So if they should really be one of the first to know if "DX13" or "DX12 Ultimate Turbo" is in the pipe and if there are real solid plans for making chiplet GPUs work. Hell they would be telling Sony/MS "hey make sure your guys build in x/y/z cause we're done with monolithic chips".

It's just weird that they would go all in on the Arch before the API was well on its way.

The alternative of course is that there was never any high end RDNA4 and the whole gen is really a pipe cleaner gen to set-up RDNA5, but who knows.

 

[moinmoin]

-I mean, it's not a thing AMD bets on, as one of the primary DGPU manufacturers and MS/Sony's console partner they are actively involved in making sure the next API will play nice with their hardware (so is Nvidia as the 800lb gorilla, of course).

So if they should really be one of the first to know if "DX13" or "DX12 Ultimate Turbo" is in the pipe and if there are real solid plans for making chiplet GPUs work. Hell they would be telling Sony/MS "hey make sure your guys build in x/y/z cause we're done with monolithic chips".

It's just weird that they would go all in on the Arch before the API was well on its way.

The alternative of course is that there was never any high end RDNA4 and the whole gen is really a pipe cleaner gen to set-up RDNA5, but who knows.

It actually is kind of an AMD/RTG tradition to implement hardware functionality before it's supported in any available API. It's also an AMD/RTG tradition to forward packaging development in DGPUs, that's how technologies like HBM came to be.

 

[GodisanAtheist]

It actually is kind of an AMD/RTG tradition to implement hardware functionality before it's supported in any available API. It's also an AMD/RTG tradition to forward packaging development in DGPUs, that's how technologies like HBM came to be.

-Fair. Point.

 

[jpiniero]

IMO, they can't release a GPU that doesn't work with DX11 or OpenGL or whatever. It has to work like a monolithic GPU.

 

[moinmoin]

IMO, they can't release a GPU that doesn't work with DX11 or OpenGL or whatever. It has to work like a monolithic GPU.

I'd imagine a chiplet based GPU as planned couldn't scale perfectly across all chiplets but would still be capable of using at least one chiplet fully for "legacy" workloads. So the issue rather would be achievable peak performance at least with some graphics workload at all, which failed to materialize thus making N41 and N42 wholly expendable. That's a good point though, maybe @adroc_thurston can chime in with further details.

 

[adroc_thurston]

It actually is kind of an AMD/RTG tradition to implement hardware functionality before it's supported in any available API

no?

using at least one chiplet fully for "legacy" workloads

Everything not CUDA/ROCm is a "legacy" workload.
Everything with graphics pipeline is legacy.

 

[jpiniero]

no?

Everything not CUDA/ROCm is a "legacy" workload.
Everything with graphics pipeline is legacy.

Be kind of hard to sell a gaming GPU without graphics.

 

[moinmoin]

It actually is kind of an AMD/RTG tradition to implement hardware functionality before it's supported in any available API.

no?

Popular example: Tesselation

 

[GodisanAtheist]

Popular example: Tesselation

-Also Primitive Shaders.

But that's a whole different ballgame than building an entire GPU arch around an API/Legacy solution that doesn't exist.

 

[adroc_thurston]

Be kind of hard to sell a gaming GPU without graphics.

Yea that's the trick with tiled graphics.

Popular example: Tesselation

TruForm was just an experiment.

-Also Primitive Shaders.

Completely unrelated thing.

 

[Tuna-Fish]

Big question is vram 12 or 16

18 might be an option for 192-bit bus, and 24 for 256-bit.

 

[jpiniero]

Yea that's the trick with tiled graphics.

Maybe we should be asking whether RDNA5 will be enough time for them to figure it out. Or will they go back to something closer to RDNA3.