Discussion RDNA4 + CDNA3 Architectures Thread

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DisEnchantment

Golden Member
Mar 3, 2017
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With the GFX940 patches in full swing since first week of March, it is looking like MI300 is not far in the distant future!
Usually AMD takes around 3Qs to get the support in LLVM and amdgpu. Lately, since RDNA2 the window they push to add support for new devices is much reduced to prevent leaks.
But looking at the flurry of code in LLVM, it is a lot of commits. Maybe because US Govt is starting to prepare the SW environment for El Capitan (Maybe to avoid slow bring up situation like Frontier for example)

See here for the GFX940 specific commits
Or Phoronix

There is a lot more if you know whom to follow in LLVM review chains (before getting merged to github), but I am not going to link AMD employees.

I am starting to think MI300 will launch around the same time like Hopper probably only a couple of months later!
Although I believe Hopper had problems not having a host CPU capable of doing PCIe 5 in the very near future therefore it might have gotten pushed back a bit until SPR and Genoa arrives later in 2022.
If PVC slips again I believe MI300 could launch before it

This is nuts, MI100/200/300 cadence is impressive.



Previous thread on CDNA2 and RDNA3 here

 
Last edited:

Frenetic Pony

Senior member
May 1, 2012
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I don't really see any difference in what you wrote and what I wrote, you just added more details.
BTW the clockspeed increase of 40%(3.5GHz vs 2.5GHz) I mentioned wasn't because of N3E but because they fixed their architecture, I didn't add any additional gains to It.

There is really nothing complicated about production cost. AMD wants It as low as possible, that's all. They will choose the cheaper option unless the costlier one offers significant advantages like higher clocks, better efficiency and so on, which would allow them to sell their product for more.
Of course, in the case of N3E demand will be high and It would be better to allocate It to more profitable products, so the GPU would be left with N4P instead.

The question still stands, which one is better to use for a relatively small monolithic chip?


N4P vs N5 provides 11% speed improvement, 18% energy reduction(22% higher power efficiency) and 6% improvement in transistor density.Videocardz
If I compare N3E FinFlex 2-1 Fin vs N4P then we end up with
+47% density, +0% speed, -15% energy reduction
I will use this one in my table.

SemiAnalysis claims 35% higher cost for N3E than N5. Let's keep It also for N3E vs N4P.
I made a table with a 27B RDNA4 GPU using different nodes with different transistor density as an example.
NodeMTr/mm2Wafer costGPU sizeGood dies per waferFaulty dies per waferPrice per good waferPrice per good+faulty wafer
N4P123 (100%)$15,000
(100%)
220mm220650$72.8$58.6
N3E
2-1 FIN
180 (147%)$20,250
(135%)
150mm232452$62.5$53.9
N3E
2-1 FIN
150
(122%)
$22,500
(150%)
180mm226551$84.9$71.2
My conclusion is that even If AMD used N3E there would be only a little gain in performance and even efficiency wouldn't be that much better.
Production cost could end up either cheaper or costlier depending on N3E's price and density improvement.

My point was just that N3E should be costlier, and not because of the generic density vs cost. The monolithic vs chiplet discussion is uninteresting for cost, both dies cost the same. Generic density is not the best cost factor estimate, because SRAM vs logic is much different in scaling terms than just MTr/mm.

Of course AMD wants the lowest cost they can get, but the interesting part is "versus what". Lowest cost is interesting because it's different from chip to chip. It's why they fab their memory bus and SRAM chips on 6nm, scaling for both analogue and SRAM drop off precipitously with newer nodes.

But if 4P is cheaper, then why would anyone want N3E? Ahh, because squeaking out the highest possible efficiency is worth the cost in some cases. The higher the cost of cooling, as in datacenter products, the more willing customers are to pay more for the initial product. But probably not for consumer GPUs where there's already tight margins, a slowly unfolding price war, and consideration for how much power GPUs use seems to take up little concern.

But! But there's also the big "Halo" product. People looove the giant halo product for GPUs, it decides who is "winning" in the lower attention span audience, and in the highest end is also the default go to, with the associated high profit margins that brings. Could "winning" be enough to offset higher production costs? Let's assume RDNA4 is monolithic and has a big "halo" product aiming to "win". Would fabbing the monolithic part on N3E be worth it there, while the smaller ones go onto 4p? It's worth considering.

So the question is interesting because it gets more complicated than just comparing $$ per MTR. Which is fun to consider.
 

jpiniero

Lifer
Oct 1, 2010
16,063
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But! But there's also the big "Halo" product. People looove the giant halo product for GPUs, it decides who is "winning" in the lower attention span audience, and in the highest end is also the default go to, with the associated high profit margins that brings. Could "winning" be enough to offset higher production costs? Let's assume RDNA4 is monolithic and has a big "halo" product aiming to "win". Would fabbing the monolithic part on N3E be worth it there, while the smaller ones go onto 4p? It's worth considering.

But that's not what appears to be going on. What's going to get released is low and very low end products.
 
Jul 27, 2020
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Who at AMD has been greenlighting these designs that are impractical to manufacture? Maybe nGreedia put a trojan executive in their midst to sabotage their GPU division.
 

adroc_thurston

Diamond Member
Jul 2, 2023
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96
presumably because they can't get it working properly in time.
Yea validating this to work with legacy graphics API is hell.
But that's a one-time only hell!
So it's was going more than 2x or even 2.5x+ perfomance than 7900XTX
I've no honest to god idea since this hadn't reached the TO.
Who at AMD has been greenlighting these designs that are impractical to manufacture?
This is very practical to make.
Very hard to validate tho.
 

jpiniero

Lifer
Oct 1, 2010
16,063
6,533
136
So they just get their engineers working on stuff without looking at all possible angles? God Bless their CPU design teams for keeping them afloat.

That's a good point. You would think that AMD would only commit to doing a chiplet design like that after having proved it in R&D first. That's probably what NV is doing.
 

adroc_thurston

Diamond Member
Jul 2, 2023
5,455
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So they just get their engineers working on stuff without looking at all possible angles?
?
But RDNA5 is going higher than canceled N41 or just same?
how would I know.
after having proved it in R&D first
what the hell is MI300 even.
That's probably what NV is doing.
No they just have no capability to do what AMD does.
Advanced packaging experts and insanio uncore designers don't grow on trees.
There's a good reason AMD is the sole driver of TSMC's advanced packaging roadmap.
 

adroc_thurston

Diamond Member
Jul 2, 2023
5,455
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