What would be his grounds for damages? That he knowingly bought a company he knew had previously made a stupid agreement?
If you buy a lemon you don't have the right to complain its a lemon.
It's probably due to the die shrink. The GPU seems to be be the same as with th 5800K, but with a 44 Mhz higher clock.
Pretty sure Richland is still 32nm, my guess is better fine tuning. As was said, Trinity tended to have a higher than necessary default voltage so there was clock headroom available with more detailed binning.
Pretty sure Richland is still 32nm, my guess is better fine tuning. As was said, Trinity tended to have a higher than necessary default voltage so there was clock headroom available with more detailed binning.
The performance increases that are being touted for Richland are due impart to some tweaked microcode, and some tweaks to GloFo's previously very problematic 32nm node.
If GloFo finally fixed their 32nm node, we could potentially see faster FX parts as well. In fact, I don't see why the boosts made to Richland are inapplicable to Vishera, but it'd be nice to have more detailed information.
Hey, I wasn't the one that came up with the theory. I'm just going off the information that's been given -- that Richland's improvements are due to them tweaking the process.330+mm^2 die clocking in at 4GHz in a 125W TDP and you are still thinking the 32nm node is borked?
Intel would love to have that kind of power and clockspeeds for a 330+ mm^2 XEON chip at 32nm.
The problem with piledriver is its microarchitecture, not the process node IMO. Getting a behemoth 330mm^2 chip to clock in at 4GHz with 125W TDP at 32nm is a miracle, second to none. Too bad it is being used to push piledriver microarchitecture instead of pushing something a little higher performing in terms of IPC/GHz like Sandy Bridge.
IMO the main problem is the massive cache on die which is there to compensate for rather under-performing memory subsystem. SR core is about to fix that with emphasis on performance per thread(they specifically mention average load latency,load to store forwarding improvements, cache power saving features etc.) . SR is probably their last chance to fix BD and make it lean and mean. If they fail ,they will not bother with EX core I'm afraid.330+mm^2 die clocking in at 4GHz in a 125W TDP and you are still thinking the 32nm node is borked?
Intel would love to have that kind of power and clockspeeds for a 330+ mm^2 XEON chip at 32nm.
The problem with piledriver is its microarchitecture, not the process node IMO. Getting a behemoth 330mm^2 chip to clock in at 4GHz with 125W TDP at 32nm is a miracle, second to none. Too bad it is being used to push piledriver microarchitecture instead of pushing something a little higher performing in terms of IPC/GHz like Sandy Bridge.
What you are referring to is L3 latency and it will remain unchanged. I'm referring to average load latency which will be drastically improved(as their HC presentation states).
Nice article about Richland up at Semiaccurate:
http://semiaccurate.com/2013/03/12/amd-goes-mobile-first-with-richland/#.UT8cDxwqysY
Most interesting thing for me is that AMD's put thermal-based Turbo into it. Explains how they can get the extra turbo headroom- should let them more accurately balance things.
Nice article about Richland up at Semiaccurate:
http://semiaccurate.com/2013/03/12/amd-goes-mobile-first-with-richland/#.UT8cDxwqysY
Most interesting thing for me is that AMD's put thermal-based Turbo into it. Explains how they can get the extra turbo headroom- should let them more accurately balance things.
the more i see about k15 family, the more i think that the first bulldozer was an alpha chip
Whooaaa. AMD has been busy. Was hoping we'd get desktop parts, though.Nice article about Richland up at Semiaccurate:
http://semiaccurate.com/2013/03/12/amd-goes-mobile-first-with-richland/#.UT8cDxwqysY
Most interesting thing for me is that AMD's put thermal-based Turbo into it. Explains how they can get the extra turbo headroom- should let them more accurately balance things.
Sure APU based on SR won't have L3, but 2014 Opteron probably will have it . BTW AMD annoucned that they will be making 64bit compatible ARM based Opteron models in 2014! This is a huge news since they will most likely also combine x86 and arm architecture in some sort of hybrid high performance/low power offerings. If these parts would to include the onboard GPU along with tiny ARM cores then it would be very interesting product, maybe just what AMD needs to get back in the server arena.Given that Kaveri is an APU, I expect it to not have and L3 (same as their current APUs). Which is one way of fixing L3 latency
Nice article about Richland up at Semiaccurate:
http://semiaccurate.com/2013/03/12/amd-goes-mobile-first-with-richland/#.UT8cDxwqysY
Most interesting thing for me is that AMD's put thermal-based Turbo into it. Explains how they can get the extra turbo headroom- should let them more accurately balance things.
Dang, looks impressive
Regarding the "rest of system" power numbers - any idea why the system would consume 1.5W less power during 720p playback for the Richland setup versus the Trinity setup?
Shouldn't the "rest of system" power usage be identical between both setups? Unless they used different setup and did not normalize this hardware aspect?
Regarding the "rest of system" power numbers - any idea why the system would consume 1.5W less power during 720p playback for the Richland setup versus the Trinity setup?
Shouldn't the "rest of system" power usage be identical between both setups? Unless they used different setup and did not normalize this hardware aspect?
Do you have a source on that? I'd be really interested in reading itTrinity itself took control of a lot of the power management for the whole system- it's these features that forced them to move to a new socket from Llano.