Okay, since no one here has yet made any technical remarks on die size, I think I'll butt in...I'm not an engineer (yet ), but I have taken multiple computer engineering and digital logic circuit design classes, so I think it makes me at least somewhat qualified to give an explanation.
As you may well know, integrated circuits are composed of logic gates (AND, OR, NOT, NOR, NAND, XOR, etc...). They perform boolean algebra operations on a digital signal; hence, you have a digital computer.
All logic gates have a certain amount of gate delay, or the time it takes for the gate to perform it's operation. For example, if you send a logic 0 through a NOT gate, it might take 1ns for the logic 1 to output.
There are two types of logic circuits: combination and sequential. Combinational circuits can be explicitly defined by its inputs, while a sequential circuit is defined by both its inputs and outputs. Thus, sequential circuits usually contain some sort of loop...sequential circuits (usually in the form of registers, which store 1 bit) are often used in combination with combinational circuits. Finally, sequential circuits (unlike combinational circuits) are tied to a clock signal; depending on the type of sequential circuit, it can only change at most once per clock cycle (most change on the positive transition of the clock signal).
Let's say that you have some circuit (part of the entire integrated circuit) that has some number of gates, such that the total gate delay is 5ns...that is, when an input is driven, it takes 5ns for the output to appear. Since you shouldn't change the input more than once per clock cycle (otherwise input might be lost), you shouldn't run the circuit faster than 1/5ns = 200 MHz. This fact is the main thing that holds back clock speeds in processors.
Now, lets say you originally designed this circuit using a .25u process. When you make the transition to .18u, the individual transistors composing the logic gates can run faster; heat is also reduced, but the increase in transistor speed is the most important factor. Thus, the total gate delay in a circuit will be lower. Now, after making the transition to .18u, let's say the total gate delay of the circuit is now 4ns. This means the circuit can reliably be run at a max speed of 250 MHz.
If you compare the same processor, one built using a .25u process, and the other at .18u, you can say that the .18u processor has the capacity to run cooler and at a higher clock rate. You cannot compare two different processors built on different processes and say that one is automatically faster than the other based on die size alone. Circuit design is by far the most important factor.