Ryzen, Skylake, and everything that's coming next. (MEGA discussion thread)

[imported_ats]

We know the perf already in ryzen between ccx and its working plently fine. We dont know inter die or socket yet but The Stilt says its up there. So its actually performing. Its evident and not only ppt slide bs.

The mythical properties you and others are shoving on to it certainly are ppt slide bs. IF is an interface specification. Nothing more, nothing less. It doesn't turn lead into gold. It won't allow a perpetual motion machine. It is subject to all the same limits and issues that affect all interfaces.

You dont seem to grasp or understand its not a simple bus standard but a framework for how they can also design gpu and cpu. Perhaps its a bit to abstract and probably goes beyond the level you have worked on it. Fair enough. Thats how progress is. And obviously you need good cpu and gpu ip also. No reason to state the obvious. Ev6 whatever is probably similar a long stretch but its excactly the extend that makes the difference.
Amd claims its major and they already have the first results to back that up. Its an excellent start but we also need eg the next tr and epyc perf to be up there.

So now it isn't a specification but a "framework" that is "abstract", lol. Seriously, step back. Intel has this revolutionary thing called marketing too. IF is an interface specification. Not a framework. Not an abstract. Any progress being made is going to be minor and limited to small details here and there. As far as details to back it up, there are literally no details out there to say that IF is useful at all as AMD has yet to release a product that would even begin to stress an interconnection network.

 

[majord]

6C 12T Coffelake will be much faster than R5 1600X both in ST and MT, but it will also be more expensive.

6C 12T Coffelake will be much faster than R5 1600X both in ST and MT, but it will also be more expensive.

Curious, has there been any confirmation of CFL-6 clockspeeds? Is there an assumption base + all-core turbo clocks will be in the realm of 7700k in the same thermal envelope? Seems very ambitious with 50% higher core count

max OC on the other hand - defiantly, but no doubt without signifcant power consumption

 

[Topweasel]

Curious, has there been any confirmation of CFL-6 clockspeeds? Is there an assumption base + all-core turbo clocks will be in the realm of 7700k in the same thermal envelope? Seems very ambitious with 50% higher core count

max OC on the other hand - defiantly, but no doubt without signifcant power consumption

Probably closer to 6700k core clocks. But it would still allow it to perform higher than the 1600x by a decent margin.

 

[Bouowmx]

From the long Intel thread, a SiSoftware entry of an Intel Coffee Lake 6 cores and Hyper-threading, 3.1-4.2 GHz: http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...core-i9-7980xe.2428363/page-478#post-38929377

No model name string, so still unfinalized?

 

[majord]

Probably closer to 6700k core clocks. But it would still allow it to perform higher than the 1600x by a decent margin.

Depends on your definition of Decent I suppose. Scaling back to 4c8t, Only 15% between a 1500x and 6700k in apps, less in 720p games according to cbase

https://www.computerbase.de/2017-04/amd-ryzen-5-test/2/?amp=1#abschnitt_anwendungen_windows

 

[Abwx]

Depends on your definition of Decent I suppose. Scaling back to 4c8t, Only 15% between a 1500x and 6700k in apps, less in 720p games according to cbase

https://www.computerbase.de/2017-04/amd-ryzen-5-test/2/?amp=1#abschnitt_anwendungen_windows

15% with a quite outdated bench...

https://www.computerbase.de/2017-04/amd-ryzen-5-test/2/?amp=1#abschnitt_anwendungen_windows

http://www.anandtech.com/show/11170...review-a-deep-dive-on-1800x-1700x-and-1700/17

 

[majord]

15% with a quite outdated bench...

Well the Cbase link is an avg of all tests.

Not sure 3dpm counts for anything at all tbh

 

[itsmydamnation]

The mythical properties you and others are shoving on to it certainly are ppt slide bs. IF is an interface specification. Nothing more, nothing less. It doesn't turn lead into gold. It won't allow a perpetual motion machine. It is subject to all the same limits and issues that affect all interfaces.

I find this kind of annoying ( just like the ryzen ECC crusade). IF actually has nothing to do with Interfaces, IF is interface agnostic. IF is a data/control plane specification. But when people say IF they are talking the entire methodology of how AMD is building the interconnects between major blocks within SOCs, between SOC's on the same package and between packages. Now what really annoys me about your 1/2 truths above is that as a part of that package of technologies they have different interface and physical implementations for those different interconnects.

The on SOC has an interconnect
The on package has GMI interconnect ( appears to be custom 16bit interfaces), according to the stilt they run 2x the clock rate of GMIx ( could be upto 25ghz)
The inter package has GMIx which runs on the DesignWare Enterprise 12G PHY, which can run Express 3.1, 40GBASE-KR4, 10GBASE-KR, 10GBASE-KX4, 1000BASE-KX, 40GBASE-CR4, 100GBASE-CR10, XFI, SFI (SFF-8431), QSGMII, and SGMII.

Now what AMD is doing that is completely different to Intel is using these common interconnects to connect major building blocks across a very broad range of building blocks all with the common dataplane/control packet (probably) based transport scheme:

Vega will use GMI to go on package with CPU
Vega uses IF for onchip interconnects
Navi will probably use IF for on package GPU cross connect
Navi will probably use IF for onchip interconnects
Zepplin uses it for onchip, on package and inter package
Any semi custom SOC's will use it

That's the differentiation between what has come before (hyper transport/QPI etc).
The other thing to recognize is that even between packages the extra latency is dominated by cache coherency not by encode/transmit/receive/decode. Zeppelin is already paying that probe/directory lookup price between the two CCX's so its likely that the only increase in latency will be the physical so we are looking at something like 15ns. Intel's latency grows with every core added. When the 6core CCX, 48 core server parts come out, intra CCX latency will probably go up a little and then every other latency will stay the same ( with all things being equal).

 

[Topweasel]

Depends on your definition of Decent I suppose. Scaling back to 4c8t, Only 15% between a 1500x and 6700k in apps, less in 720p games according to cbase

https://www.computerbase.de/2017-04/amd-ryzen-5-test/2/?amp=1#abschnitt_anwendungen_windows

It can go back and forth but the point is higher IPC, higher clocks (probably), same amount of cores. If looking purely at CPU out put for a 6 core design and not counting platform costs, very specific use cases and so on. A 6c12t unlocked chip will be a faster CPU by a measurable margin than a 1600x.

 

[imported_ats]

That's the differentiation between what has come before (hyper transport/QPI etc).

Except that what's come before HAS either done that or can do that. Using a protocol layer on a different physical layer, been done. Using a transport layer on multiple different physical layers, been done. It appears that ignorance of what has already been done is causing people to think that IF is something completely new and revolutionary, but it isn't. It is an interface specification that like literally every interface specification has multiple layers with multiple hand off points.

The other thing to recognize is that even between packages the extra latency is dominated by cache coherency not by encode/transmit/receive/decode. Zeppelin is already paying that probe/directory lookup price between the two CCX's so its likely that the only increase in latency will be the physical so we are looking at something like 15ns. Intel's latency grows with every core added. When the 6core CCX, 48 core server parts come out, intra CCX latency will probably go up a little and then every other latency will stay the same ( with all things being equal).

No, going off chip involves significantly more than enc/xmit/rcv/dec. As far as on chip latencies, CCX also isn't revolutionary, in fact multiple vendors including Intel ship or have shipped clustered core cache coherent designs. They have advantages and disadvantages just like everything else.

 

[krumme]

IF can include eg tools and processes for development and production. We dont know.
Nobody says it needs to be revolutionary. You keep repeating that strawman. Who cares eg how many patent is used making it. What matters is the results as can be seen in products but also more importantly development cost and TTM.
We will see how epyc socket to socket performs and especially how many new products amd can launch the next few years. That will say a good deal about how effective IF was formed.

 

[Oddzz]

on the other end of the spectrum. Has there been any indication that Banded Kestrel will ever come to AM4? or are we only going to see harvested Raven Ridge to fill the low end?

Seems it would be potentially extremely competitive with intel's i3 and Celeron line.

Banded Kestrel will be the Ryzen/Vega APU for desktops, right? If that's the case then it will ship in the first half next year after they launched the RyzenMobile platform later this year.

Listen to this (skip to ~10:45) where Jim Anderson talks about that.

 

[Abwx]

Well the Cbase link is an avg of all tests.

Not sure 3dpm counts for anything at all tbh

In the average, and if the bench was updated, it should be 11% instead of 15% .

 

[T1beriu]

Has there been any indication that Banded Kestrel will ever come to AM4?

There has not been any indication and I can't see it happening because Banded Kestrel is an ultra low power (4-15W) APU that uses a BGA socket (FT5), something that doesn't really have a place or a socket in a desktop platform.

I think that the Banded Kestrel is only for tablets, slim laptops/convertibles, small bricks and embedded devices.

Seems it would be potentially extremely competitive with intel's i3 and Celeron line.

I think Raver Ridge with half of its cores (CPU + GPU) disabled will compete against that.

Banded Kestrel will be the Ryzen/Vega APU for desktops, right?

No.

 

[majord]

In the average, and if the bench was updated, it should be 11% instead of 15% .

Get what you're saying now. Though quite an outlier.

Still, I was being conservative, a 1500x is clocked lower than 1600x

Banded Kestrel will be the Ryzen/Vega APU for desktops, right? If that's the case then it will ship in the first half next year after they launched the RyzenMobile platform later this year.

Listen to this (skip to ~10:45) where Jim Anderson talks about that.

thanks , doesn't actually mention anything about client. was an interesting listen though.

There has not been any indication and I can't see it happening because Banded Kestrel is an ultra low power (4-15W) APU that uses a BGA socket (FT5), something that doesn't really have a place or a socket in a desktop platform.

I can't see anything on the SoC (concept) diagram that suggests it couldn't be placed on AM4 - it is basically just a half Raven ridge. It's a zen core at heart, the fact the embedded version is targeted at 4-15w, doesn't mean it can't scale to 35-45w for desktop.

 

[iamgenius]

That's how it always is per socket Intel has had a Launch CPU and then a Refresh CPU. The z270 may have just come out, but it's the same socket as the z170. So people who got a 6700k can upgrade without replacing their board to a 7700. But yeah anyone jumping on the 270 7700 bandwagon, were always immediately at a dead end.

[H] says otherwise. It will be 1151, however, that doesn't guarantee it will compatible with z270 !

https://hardforum.com/threads/coffe...odels-planned.1930226/page-10#post-1043046398

 

[Topweasel]

[H] says otherwise. It will be 1151, however, that doesn't guarantee it will compatible with z270 !

https://hardforum.com/threads/coffe...odels-planned.1930226/page-10#post-1043046398

Not supporting any previous chips is for all intents a new socket. Like 2011 v1-v3.

 

[jpiniero]

Not supporting any previous chips is for all intents a new socket. Like 2011 v1-v3.

Presumably at this point the 300 series does support Kaby Lake and also possibly Skylake. But Coffee Lake will require using the 300 series. So it's backwards but not forwards compatible.

I would not expect Icelake to support this socket.

 

[moinmoin]

Since this thread turned into the main place for Infinity Fabric (<3) discussion I wanted to share following older article with guesses on its origin, potential and limitations (it essentially starts out as a summary of the AMD Financial Analyst Day with some history before going into the interesting stuff):
https://www.nextplatform.com/2017/05/17/amd-disrupts-two-socket-server-status-quo/
The core point is that's it's no coincidence that Epyc as announced appears to max out as two socket system. IF is a NUMA system, and the author claims the origin has been ATi's server chipset work for Opteron 6000, both maxing out at 64 nodes/cores.

 

[Ajay]

Presumably at this point the 300 series does support Kaby Lake and also possibly Skylake. But Coffee Lake will require using the 300 series. So it's backwards but not forwards compatible.

I would not expect Icelake to support this socket.

Socket or chipset? It would be sad if Ice Lake would work, at least, on the X390.

 

[krumme]

Since this thread turned into the main place for Infinity Fabric (<3) discussion I wanted to share following older article with guesses on its origin, potential and limitations (it essentially starts out as a summary of the AMD Financial Analyst Day with some history before going into the interesting stuff):
https://www.nextplatform.com/2017/05/17/amd-disrupts-two-socket-server-status-quo/
The core point is that's it's no coincidence that Epyc as announced appears to max out as two socket system. IF is a NUMA system, and the author claims the origin has been ATi's server chipset work for Opteron 6000, both maxing out at 64 nodes/cores.

Its a very nice article but i cant see the technical arguments that its a limitation/derivation from the old opteron chipset?

I think he omits that ryzen consist of 2 ccx and in many ways behaves as a numa like system from the let go.

 

[moinmoin]

Its a very nice article but i cant see the technical arguments that its a limitation/derivation from the old opteron chipset?

I think he omits that ryzen consist of 2 ccx and in many ways behaves as a numa like system from the let go.

Yeah, it's definitely lacking in that regard. I just liked the suggestion as it does make sense. AMD had been working with NUMA designs for long, ATi also contributed knowledge in that area, AMD started modularizing all their designs when creating Bulldozer, with the console SoC AMD even worked with what amounts to the 2 CCX split before it existed, and IF has become the glue that holds everything together. Naples fits as a plan from the start to make the most of the current Zen die's (and maybe more importantly its uncore's) capabilities. I guess we will see whether that's an actual limit whenever an Epyc system with more than two sockets appears.

 

[krumme]

Yep it is interesting how it scales. The size of the epyc solution is also interesting. Perhaps epyc in standard atx format?

 

[tamz_msc]

Global Foundries announces 7nm LP volume production in H2 2018.

 

[LTC8K6]

How does GF 7nm compare to Intel 10nm?