Ryzen: Strictly technical

[latentexistence]

Over at Overclock.net there's a quote (for which I can't find the source) that refers to the 1700 having a "fused package power limit of approximately 90W electrical" which does not apply to the 1700x / 1800x.

If there is a hardware limit on power draw does this mean that my 1700 running at 3.8GHz will throttle and never reach the same performance as a 1700x at the same frequency?

 

[IEC]

Over at Overclock.net there's a quote (for which I can't find the source) that refers to the 1700 having a "fused package power limit of approximately 90W electrical" which does not apply to the 1700x / 1800x.

If there is a hardware limit on power draw does this mean that my 1700 running at 3.8GHz will throttle and never reach the same performance as a 1700x at the same frequency?

Pretty sure that's wrong, considering I've run a 1700 @ 4GHz fully loaded with BOINC on all 8c/16t... which would easily be over 90W electrical.

I did not see any throttling.

 

[nix_zero]

anybody can detail how many pci-e lanes got zeppelin? from x399 data looks like that 24 lanes its an am4 socket limit, not zeppelin one but amd PPR documentation reports only "Two 8x16 PCIe® controllers supporting Gen1/Gen2/Gen3. Note that SATA Express is supported by combining an x2 PCIe port and two SATA ports on the same 2 lanes." which its not exactly clear

 

[latentexistence]

Pretty sure that's wrong, considering I've run a 1700 @ 4GHz fully loaded with BOINC on all 8c/16t... which would easily be over 90W electrical.

I did not see any throttling.

That's what I thought. It's the "fused" and "electrical" that seem odd. I read it as the power supply is fused but perhaps it means the configuration is fused in, and that's the part that is disabled in OC mode anyway.

 

[zir_blazer]

anybody can detail how many pci-e lanes got zeppelin? from x399 data looks like that 24 lanes its an am4 socket limit, not zeppelin one but amd PPR documentation reports only "Two 8x16 PCIe® controllers supporting Gen1/Gen2/Gen3. Note that SATA Express is supported by combining an x2 PCIe port and two SATA ports on the same 2 lanes." which its not exactly clear

The Stilt mentioned that Zeppelin has 2x16 in one of his previous Posts, which also matches the 128 total lanes that the Naples quad MCM can do. However, in AM4, only 24 are in use. The 1x16 which can be bifurcated to 8x/8x in X300/X370 platforms, and from the other 1x16, 8 lanes seem to be totally unused. The used 8 are bifurcated as 4x/4x, 4 for Chipset (But usable as standard PCIe in a X300 platform with no Chipset), and from the other 4, two are partially mixed with a SATA Controller (A la Intel Flex IO). I think I didn't saw an AM4 Motherboard that makes use of a PCIe 4x slot with those 4 lanes, they usually provide SATA or NVMe with these and instead get the Chipset to provide a 4x 2.0 slot.

 

[majord]

Over at Overclock.net there's a quote (for which I can't find the source) that refers to the 1700 having a "fused package power limit of approximately 90W electrical" which does not apply to the 1700x / 1800x.

If there is a hardware limit on power draw does this mean that my 1700 running at 3.8GHz will throttle and never reach the same performance as a 1700x at the same frequency?

Not at all.

 

[scannall]

Stilt, at which point are the diminishing returns just not worth it? From what I'm reading anyway, 3200 with tight timings is ideal? Better than 3600 with looser ones for instance.

 

[moinmoin]

Thankfully, I have Windows XP running 16-bit properly with a Linux Mint host running as a guest on Windows 10 with the necessary performance, sound, and disk access - with all of my data pipes functioning... so it's not a loss (phew), it's just a matter of a little hidden Linux in the background (since the machine is nearly always just suspended).

AGESA 1.0.0.6 reportedly fixed the VME bug. Can anybody here confirm?

 

[ArtForz]

I think I didn't saw an AM4 Motherboard that makes use of a PCIe 4x slot with those 4 lanes, they usually provide SATA or NVMe with these and instead get the Chipset to provide a 4x 2.0 slot.

How about Asrock AB350 Pro4 and AB350 Gaming K4? CPU x4 is muxed to either the second x16 mechanical slot or m.2.

 

[zir_blazer]

AGESA 1.0.0.6 reportedly fixed the VME bug. Can anybody here confirm?

Didn't hear any mention of VME being fixed already in latest AGESA. If they did actually fix it, it means that only the NPT bug remains.

How about Asrock AB350 Pro4 and AB350 Gaming K4? CPU x4 is muxed to either the second x16 mechanical slot or m.2.

http://www.asrock.com/mb/AMD/AB350 Pro4/#Specification
Good find. At least the AB350 Pro4 (Didn't checked the other) has a 16x/4x coming from the Processor itself. That means that it is possible to use a X370 to have 8x/8x/4x with SLI/Crossfire + PCIe SSD. It would be a serious powerhouse.

 

[IEC]

Didn't hear any mention of VME being fixed already in latest AGESA. If they did actually fix it, it means that only the NPT bug remains.

VME bug is getting fixed with 1.0.0.6 updates:
https://www.heise.de/newsticker/mel...IOS-Updates-patchen-auch-VME-Bug-3732056.html

 

[zir_blazer]

VME bug is getting fixed with 1.0.0.6 updates:
https://www.heise.de/newsticker/mel...IOS-Updates-patchen-auch-VME-Bug-3732056.html

I don't get the details of how they fixed it. Did AGESA disable the VME CPUID flag (Which was the workaround) a la Haswell TSX, or was there a proper fix so people can use VME as intended? Since AMD didn't speaked about it, details are lacking. They must be keeping low profile because that bug could scare enterprise consumers for the upcoming Naples launch.
In addition, there is this.

I just hope that they can patch everything and get a solid, stable, entirely functional product. Ryzen and Naples can finally crack the near absolute monopoly that Intel has in CPUs. So far, for a new architecture and considering how complicated x86 is, I think AMD is doing well enough.

 

[VirtualLarry]

https://www.pcper.com/reviews/Processors/AMD-Ryzen-and-Windows-10-Scheduler-No-Silver-Bullet

 

[Pick2]

VirtualLarry https://www.pcper.com/reviews/Processors/AMD-Ryzen-and-Windows-10-Scheduler-No-Silver-Bullet

Date: March 10, 2017 , Old news ?

 

[Dresdenboy]

I don't get the details of how they fixed it. Did AGESA disable the VME CPUID flag (Which was the workaround) a la Haswell TSX, or was there a proper fix so people can use VME as intended? Since AMD didn't speaked about it, details are lacking. They must be keeping low profile because that bug could scare enterprise consumers for the upcoming Naples launch.
In addition, there is this.

I just hope that they can patch everything and get a solid, stable, entirely functional product. Ryzen and Naples can finally crack the near absolute monopoly that Intel has in CPUs. So far, for a new architecture and considering how complicated x86 is, I think AMD is doing well enough.

This bug is related to 16b real mode. There might be a few, but not many big players relying on such old software.

 

[itsmydamnation]

This bug is related to 16b real mode. There might be a few, but not many big players relying on such old software.

If they are using something really old (pre XP) chances are they using some old ass ISA/PCI card and they probably don't have it vitalized. Every really old ass system i have ever seen has been attached to some kind imaging/manufacturing/building management machinery.

 

[looncraz]

AGESA 1.0.0.6 reportedly fixed the VME bug. Can anybody here confirm?

Literally the first thing I checked after updating to 1006 a couple weeks ago. Still a no go, ntvdm 100%, nothing runs. However, that's better than it was. Before, ntvdm would only randomly launch, then it would just never launch again. Now I can have multiple ntvdm processes running maxing out the CPU. Safe mode video is also a no-go.

I just don't get why it works when I run it inside of a Linux VM (still haven't run it natively... which is silly, since I have Linux Mint as a secondary bootable OS).

 

[Dresdenboy]

Literally the first thing I checked after updating to 1006 a couple weeks ago. Still a no go, ntvdm 100%, nothing runs. However, that's better than it was. Before, ntvdm would only randomly launch, then it would just never launch again. Now I can have multiple ntvdm processes running maxing out the CPU. Safe mode video is also a no-go.

I just don't get why it works when I run it inside of a Linux VM (still haven't run it natively... which is silly, since I have Linux Mint as a secondary bootable OS).

IIRC you were the first, who reported such problems. How about contacting AMD and getting some free test systems to help them out?

 

[moinmoin]

I just don't get why it works when I run it inside of a Linux VM.

The OS/2 museum article on the topic mentions that masking out the VME CPUID bit is sufficient as most software doesn't actually require VM86 VME. I'd have guessed that's what AGESA 1.0.0.6 did. For Linux it seems a change in kernel 4.3 in 2015 made the capability to put the CPU into VM86 optional so unless specifically enabled VMs are relying on emulation instead since, so VME calls never actually pass through to Ryzen.

 

[Panino Manino]

May I ask something unreasonable?
Thinking past Zen, what could be improved in Zen+?
What are the deficiencies that Zen does have now and need to be fixed ASAP.
Zen+ will push the architecture forward in what direction?
Can I expect a good jump in IPC for Zen+ over Zen? Or is this just a brief moment of luck for AMD?

 

[scannall]

May I ask something unreasonable?
Thinking past Zen, what could be improved in Zen+?
What are the deficiencies that Zen does have now and need to be fixed ASAP.
Zen+ will push the architecture forward in what direction?
Can I expect a good jump in IPC for Zen+ over Zen? Or is this just a brief moment of luck for AMD?

Being a brand new architecture, there is always some low hanging fruit. So there will likely be a decent IPC uptick. How much? I doubt anyone outside of AMD can tell you that. The current process they use is an energy efficient one, with a pretty hard wall at 3.9 to 4.1 Ghz, depending on how lucky you are at the silicon lottery. As a *guess*, they will move from LPP to LPU which should give a little more clock room, at the cost of a little more energy use. It's a good product, with room to grow.

 

[tential]

May I ask something unreasonable?
Thinking past Zen, what could be improved in Zen+?
What are the deficiencies that Zen does have now and need to be fixed ASAP.
Zen+ will push the architecture forward in what direction?
Can I expect a good jump in IPC for Zen+ over Zen? Or is this just a brief moment of luck for AMD?

This is the largest reason why I don't want Zen. It's like a rough draft. I already have a good processor, I want to see Zen 2 or even 3. I'm expecting a lot out of Zen+.

 

[looncraz]

IIRC you were the first, who reported such problems. How about contacting AMD and getting some free test systems to help them out?

Not the first time I'd be the first to discover an AMD bug

Now I just need to find someone who wants to buy Thread Ripper... I have two or more buyers for a good Zen-based APU (those are always easy sales thanks to HTPCs). My retirement is going well... LOL!

 

[Shivansps]

Ive run intro the VME bug myselft with PXE chainload on Windows 10... so 1006 should have fixed a few things?

 

[Atari2600]

As a *guess*, they will move from LPP to LPU which should give a little more clock room, at the cost of a little more energy use.

I hope they run on both.

Many core CPUs will benefit more from LPP, whereas lower-cored want the faster process.