Zen/Zeppelin seem obviously geared towards absolute power savings. The decision to tightly couple the IMCs and uncore was a move for efficiency of data transfer, and this appears to corroborate with Zen's considerably higher actual vs. theoretical sustained transfer compared to Intel's products. I think that just about every piece of that silicon was designed with a goal of meeting or exceeding the power characteristics, with few exceptions, Intel is currently capable of while still on an inferior node. This has created a chip with great potential in deployments scaling from a workstation to massive clusters, great potential going forward.
Zen is AMD's Core2/Nehalem in a sense.
My assumptions:
The GMI/IMC (and coupled PCIe/BCLK strap) is clearly the major limiting factor for this design for home users. Zen2 will again not "win" in the home/gamer market unless AMD had planned on significantly revamping the chips clock domains.
Zen2 certainly won't be on 14LPU (at first), much too late in the design phase. No easy 10% clock improvement there.
2x inter-CCX > 1x IMC speeds may be a pipe dream for Zen F4 stepping, but man would that solve a heck of a lot of latency issues (while skyrocketing uncore power draw)
The Stilt, have you gotten your hands on any other 1800x samples to compare Vmin/Fmax? Would be interesting to see possible ranges of binning for a single SKU.