Isn't the benefits of fabbing tiny die on 7nm late 2018 greater than increasing core #? From what we see, there are many more masking operations needed for 7nm than 14nm, at least before EUV is used. One would imagine defect management will be an issue. I think the greatest possibility is staying with a 4 core enhanced IPC CCX and pushing the clocks.
A ~ (100-110)mm^2 Zen2 8 core @ 4.5-5.0+ GHz would be a very attractive product.
We are going to see the real ambition of AMD with zen2 (not Zen+ pinnacle ridge H1 2018).
Im hoping for some major improvements to uarch, AVX256, maybe double L2, 12mb L3, 6 core CCX, 4x SMT, increase in execution units making the core wider? Maybe some special low latency optimised hbm L4 cache for sever or on CCX for APU?
If that gives 15℅ IPC lift, plus an 15-20℅ increase in SMT yield and a 10℅ clock increase over pinnacle ridge for a little more power consumption that would be awesome on 7nm.
Hopefully some improvements to infinity fabric bandwidth and latency as icing on the cake.
I hope they don't go the cheap easy route by keeping 4 core CCX and same width cores to increase clock speed, as we know clocks won't go much higher than 5ghz down the road as processes are scaling better with power consumption than frequency increase, it would be short sighted to have minor IPC bump and push clocks, if they make a wider core that will scale better imo.
Obviously they would have internal modelling and projections of the right Balance, I just hope if there if a close call and a clear choice to make from keeping a moderately wide core and pushing clocks with process or going wider core and minimum clock increase they will take the latter option.
Only if it makes sense of course.