It's really all we have now that the boost is so good First time I've seen decreasing a voltage to be the correct move for higher clocks.
The issue which people might be facing with undervolting is the vast difference between the cores.
Check out the voltage the CPU calculates for the best core and the worst core, on this CPU:
The best core (core 2):
The worst core (core 7):
100mV difference.
Interesting, so you are setting process affinity here? For some reason I was assuming that the CPU might not necessarily even boost the worst cores up to 4.35 GHz. But I guess it can't pick and choose what core the OS wants to run something on, and it should behave the same in terms of clock speed regardless of what the OS chooses.
I'd like to understand why the negative offset voltage makes the boost algorithm choose to use higher frequencies in the first place. I don't have enough of an understanding of it to tell if it's a quirk of my particular board or what. Before applying the offset I was a little disappointed in the behavior of the boost on my sample, wouldn't hold 4.35 on one core load and really still won't, though it at least touches it every once in a while.
One of the last patches for Civ 6 brought some performance changes. You cannot compare results from different game versions.What happened to the Civilization AI test on Tomshardware? All CPUs are listed at least 30% faster compared to any previous reviews. They get 12 seconds for a stock 1800X, while mine needs about 18.5 seconds (either stock or OCed to 3.95). No way of comparing the 2700X with the 1800X or 8700K with that data.
Too bad, because everyone else keeps listing FPS only for these games, while in practice I have to wait half a minute for Total War's AI to finish its turns.
I think that is very unlikely. It would make the IF topology a LOT more complex, pretty much a ground up redesign. Not saying no way, no how. Just very unlikely.One thing I am noticing from the VRM on some of the high-end X470 boards is they are extremely overkill.
http://www.overclock.net/forum/27199649-post2954.html
https://www.hardwareluxx.de/community/f12/pga-am4-mainboard-vrm-liste-1155146.html
Could it be that Ryzen 2 next year will have 12 core CPUs for the desktop platform?
One thing I am noticing from the VRM on some of the high-end X470 boards is they are extremely overkill.
Could it be that Ryzen 2 next year will have 12 core CPUs for the desktop platform?
Unless the CCX would grow to 6 cores, as I suppose it is "destined to" grow in 7nm While 3 CCX complexes would complicate things, two bigger ones would largely not affect the overall design - after all CCXs are connected to IF by L3 cache and you would simply add cores and connect them to L3 cache on the other end. It is by no means trivial task, as you would need to rearrange parts to keep rectangular shape of the whole CPU but since they are doing it for 7nm, maybe they would be able to do it for 12nm as well It is also not outside the realm of possibilities that it would be an early high risk production on 7nm - with a right price as Intel 8-core part will probably be much pricier then 8700K.I think that is very unlikely. It would make the IF topology a LOT more complex, pretty much a ground up redesign. Not saying no way, no how. Just very unlikely.
Asus X470-Pro, 2700X. Booted this morning for first time, everything on Auto, core voltage was at 1.4+. Set negative offset, but it is still high, needs more tweaking.
My 1700 / AB350 Gaming 3 is set with negative offset and all core at 36.25 multiplier, no stability issues.
I am using the latest version myself and measure around 18.5 seconds on a 1800X (OC or stock), which already is a bit faster than all the older reviews' results. But 12 seconds would be a huge jump in performance that I am not getting here.One of the last patches for Civ 6 brought some performance changes. You cannot compare results from different game versions.
I am using the latest version myself and measure around 18.5 seconds on a 1800X (OC or stock), which already is a bit faster than all the older reviews' results. But 12 seconds would be a huge jump in performance that I am not getting here.
Does the GPU impact AI performance? If so then spending any kind of money on a new CPU would be rather useless in comparison.
Can anyone test XFR2 using Total War (Warhammer)? This game is completely bottlenecked (maxed out core) by its main-thread, to the point where AI calculations can drop the frame-rate. But on the other hand XFR on the 1800X does absolutely nothing for it, because all the small low load extra threads keep the 1800X at a 3.7 GHz maximum (aka no boost to 4.1 GHz for that bottlenecking main thread). If XFR2 can handle these situations better then it's a real incentive to switch a Zen to a Zen+.
I am using the latest version myself and measure around 18.5 seconds on a 1800X (OC or stock), which already is a bit faster than all the older reviews' results. But 12 seconds would be a huge jump in performance that I am not getting here.
Does the GPU impact AI performance? If so then spending any kind of money on a new CPU would be rather useless in comparison.
Can anyone test XFR2 using Total War (Warhammer)? This game is completely bottlenecked (maxed out core) by its main-thread, to the point where AI calculations can drop the frame-rate. But on the other hand XFR on the 1800X does absolutely nothing for it, because all the small low load extra threads keep the 1800X at a 3.7 GHz maximum (aka no boost to 4.1 GHz for that bottlenecking main thread). If XFR2 can handle these situations better then it's a real incentive to switch a Zen to a Zen+.
That's nice and dandy, but boosting all cores to a lower frequency instead of boosting two cores to a higher frequency doesn't help much with software that bottlenecks on one or two cores.It's already doing that, it's will boost to upmost limit, that is why in review some all core boost can reach to 4,2 ghz.
That's nice and dandy, but boosting all cores to a lower frequency instead of boosting two cores to a higher frequency doesn't help much with software that bottlenecks on one or two cores.
Which is quite a let-down. Single - or rather dual - core boost should be able to hit higher frequencies and thus benefit all the myriads of apps that only make use of 1-2 cores worth of load.The point is that the 4.2 ghz all core boost is barely below the maximum single core boost.
In practice you ofen have one thread maxing out one single core while all the other threads and processes sum up to one or one-and-a-half more cores worth of utilization. Running two cores at high frequency then speeds up that one-core bottlenecking thread without slowing down all the others.Moving all of the thread to two cores just to get a higher clock on those two cores also limits performance because those two faster cores need to do all that extra work.
Which is quite a let-down. Single - or rather dual - core boost should be able to hit higher frequencies and thus benefit all the myriads of apps that only make use of 1-2 cores.
It's already doing that, it's will boost to upmost limit, that is why in review some all core boost can reach to 4,2 ghz.
Unless the CCX would grow to 6 cores, as I suppose it is "destined to" grow in 7nm While 3 CCX complexes would complicate things, two bigger ones would largely not affect the overall design - after all CCXs are connected to IF by L3 cache and you would simply add cores and connect them to L3 cache on the other end. It is by no means trivial task, as you would need to rearrange parts to keep rectangular shape of the whole CPU but since they are doing it for 7nm, maybe they would be able to do it for 12nm as well It is also not outside the realm of possibilities that it would be an early high risk production on 7nm - with a right price as Intel 8-core part will probably be much pricier then 8700K.
1. Cores inside CCX are not connected to each other, they are only connected to L3 cache - so only 2 additional links to L3 cache would be needed. https://www.custompcreview.com/wp-content/uploads/2017/06/amd-ccx-epyc-cpu-presentation-slides-1.jpg - there you can see 6 links inside L3 cache and 4 links from L3 to L2 cache. If anything adding 2 cores would add 5 or 9 additional links between cache slices depending on if you wanted to keep each other to each other philosophy. It would also be nice to add another 8MB cacheI would imagine that AMD would not want to change the CCX design itself for ZEN anytime soon. The 4 cores in each CCX are effectively directly connected to each other, the shared L3 in the CCX, and the port to the IF for the whole chip. That's 5 high speed links per core. If you increase the CCX count to 6, that gives each core 7 total links, with 5 links from each core crossing the CCX to get to the other cores. The CCX gets a LOT more complicated as it goes from having 6 inter-procesor links to 12, doubling them. It also degrades the CCX L3 cache efficiency unless you also increase it by 50%, increasing the size of the whole CCX further. This will result in having to rearrange the functional units in the die. Having larger CCXs means that they will have greater requirements to communicate between them. this will likely require that the IF be modified to increase it's ability to transmit data between the CCXs.
The alternative is to rearrange the functional units in the die to accommodate a third CCX. The CCX designs can be retained (save for any internal core changes that can be essentially done once and copied through the rest) to keep the shrink simple. What gets more complicated? An additional port is needed in the IF, which was designed as a flexible, adaptable interconnection logic in the first place. That's basically it, aside from some internal chip management logic being tweaked to support it. What are the drawbacks? The IF will be more heavily utilized by inter CCX communications. This can be alleviated by increasing the speed or width of the IF pathways. That's not going to be the simplest of things to be sure, but, it will not only help with inter CCX communications, but it can also help with communication latency between the CCXs and the PCI bus, memory controllers, etc.
So, what we have is both approaches requiring the IF to be modified to accommodate them properly, both approaches requiring the die to get a new floor plan, and both impacting the multi-chip package interconnect traffic (more cores, more cross talk). One requires a major tear up of the CCX, the other just requires that a third one be added. If AMD is as resource strapped as they appears to be, which route do you think that they would take?
My guess is that they are going to make slight tweaks to the cores themselves, they will add a third CCX (probably rotating them 90 degrees and lining them up side by side), and they will increase the ability of the IF to move data around inside of the chip. I'd imagine that there will also be a new DRAM controller, likely with either faster DDR4 or maybe in a later revision, DDR5 support (though, I feel that that will require a new socket revision, like AM4+).
Hardware.info had a similar synopsis on Vega. The tipping point of Poole-Frenkel Effect is rather steep and no buffering is being spared by the driver. I like it that undervolting yields get easier to plot.It's really all we have now that the boost is so good First time I've seen decreasing a voltage to be the correct move for higher clocks.
And you mean that running 2 cores at 4.7 Ghz draws more power than running 8 cores at 4.2 GHz (and the rest idle/parked)?