I would imagine that AMD would not want to change the CCX design itself for ZEN anytime soon. The 4 cores in each CCX are effectively directly connected to each other, the shared L3 in the CCX, and the port to the IF for the whole chip. That's 5 high speed links per core. If you increase the CCX count to 6, that gives each core 7 total links, with 5 links from each core crossing the CCX to get to the other cores. The CCX gets a LOT more complicated as it goes from having 6 inter-procesor links to 12, doubling them. It also degrades the CCX L3 cache efficiency unless you also increase it by 50%, increasing the size of the whole CCX further. This will result in having to rearrange the functional units in the die. Having larger CCXs means that they will have greater requirements to communicate between them. this will likely require that the IF be modified to increase it's ability to transmit data between the CCXs.
The alternative is to rearrange the functional units in the die to accommodate a third CCX. The CCX designs can be retained (save for any internal core changes that can be essentially done once and copied through the rest) to keep the shrink simple. What gets more complicated? An additional port is needed in the IF, which was designed as a flexible, adaptable interconnection logic in the first place. That's basically it, aside from some internal chip management logic being tweaked to support it. What are the drawbacks? The IF will be more heavily utilized by inter CCX communications. This can be alleviated by increasing the speed or width of the IF pathways. That's not going to be the simplest of things to be sure, but, it will not only help with inter CCX communications, but it can also help with communication latency between the CCXs and the PCI bus, memory controllers, etc.
So, what we have is both approaches requiring the IF to be modified to accommodate them properly, both approaches requiring the die to get a new floor plan, and both impacting the multi-chip package interconnect traffic (more cores, more cross talk). One requires a major tear up of the CCX, the other just requires that a third one be added. If AMD is as resource strapped as they appears to be, which route do you think that they would take?
My guess is that they are going to make slight tweaks to the cores themselves, they will add a third CCX (probably rotating them 90 degrees and lining them up side by side), and they will increase the ability of the IF to move data around inside of the chip. I'd imagine that there will also be a new DRAM controller, likely with either faster DDR4 or maybe in a later revision, DDR5 support (though, I feel that that will require a new socket revision, like AM4+).