Samsung and GLOBALFOUNDRIES Forge Strategic Collaboration to Deliver 14nm FinFET

[Ajay]

Don't confuse tape-out with customer orders. Tape-out is just a design milestone.

I'm not. IIRC, tape-outs, now-a-days, means a sample run in silicon. It used to just mean the design was ready to go to the fab (literally on mag-tape). So, GF could have pending orders waiting on a successful tapeout, but no hard orders yet if their process is still too immature. I'm just reaching for straws here - trying find out what is going on at Malta.

IDC indicates that Samsung are dragging their feet a bit on 14 nm, so that's one mystery solved, but is going on with 20nm?

GF recently hired a new CEO, specifically to take on the Malta challenge - http://www.bizjournals.com/albany/m...m-to-take-ny-plant-to-new-level.html?page=all. But I'm having trouble find out if GF is just having technical problems like TSMC or if 20nm was pretty much busted like 14XM was.

 

[NostaSeronx]

Seems Fab 8 is still in the ramp up stage for wafer production.

The funny bit is that GlobalFoundries upgraded Fab 1 for 20-nm and 14-nm production. That is where the initial yields from Qualcomm, Broadcom, and AMD will be at.

The issues with Fab 8 and uncertainty with the other Fab (x)s. Caused the freeze of the Abu Dhabi foundry and the upgrades to Fab 1 and Fab 7.

 

[mrmt]

That and FUSI is the only way to get gate last for SOI. Then, you have CEA-Leti using IBM's patents for partially silicided gates for 28nm/14nm FDSOI. Finally, with 10nm FDSOI using fully silicided gates.

The Electronic division contribution was 68% of consolidated sales (against 98% last year) at 167.5 million Euros or - 34.9% from last year (-32.3% at constant exchange rate). 300mm wafer sales, which accounted for 54% of total Electronic sales in 2012-2013, were down by 57.2% in value because PDSOI technology end of life started to materialize as well as a result of excess inventories for game consoles markets. Over the 2013-2014 fiscal year, 300 mm wafer sales represented 36% of the Electronic division’ sales.

(...)

The Group is now anticipating a more balanced contribution from its electronic and Solar Energy Divisions over its new financial year. In the Electronic segment, demand for mobility and RF applications should offset the definitive end of life of PDSOI technologies. The most recent forecast anticipates a significant sequential decrease in Q1 compared to Q4 (i.e. -45%) followed by sustained growth over the rest of the fiscal year as a result of first significant deliveries of FDSOI technologies and continued deliveries of RF applications. Overall electronic sales are anticipated to be almost stable over the 2014-2015 financial year.

Yet another business in free fall. But I'm sure we'll soon see a XXnm SHP FUSIFDUTBSOI node developed from arcane CEA-LETI/STM/IBM patents to dominate the market, won't we?

 

[NostaSeronx]

Yet another business in free fall. But I'm sure we'll soon see a XXnm SHP FUSIFDUTBSOI node developed from arcane CEA-LETI/STM/IBM patents to dominate the market, won't we?

Most of the patents are at IBM which CEA-Leti and STMicro have to pay royalties for.

FDSOI + ET/UTBB + FUSI equals cost viable "Strained Si Directly On Insulator(SSDOI)." https://en.wikipedia.org/wiki/Strained_silicon_directly_on_insulator
https://www.google.com/patents/US20140008729
https://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6242489

IBM and GlobalFoundries' 16nm ETSOI is SSDOI.
CEA-Leti and STMicroelectronics 28/14 UTBB FDSOI is SOI, with 10nm UTBB FDSOI being SSDOI.

If STMicro calls their "14nm FDSOI" solution "14nm" then it makes sense for IBM/GloFo to call their solution "16nm." Since, there is only a 2-nm difference in gate lengths.

STMicroelectronics' SOI:

^-- from 2009.

 

[xpea]

Another fun fact: Nvidia's out of the smartphone game, so your little fun fact has no relevance.

you are irrelevant and useless to this topic. since when 20nm or any node is only used on phones ?

 

[Homeles]

you are irrelevant and useless to this topic. since when 20nm or any node is only used on phones ?

There's a word called context that you should probably look up the definition of. Your comment was nonsensical given the preceding comments in the thread. In fact, Intel17 specifically mentioned that Nvidia was out of the smartphone game in his comment, yet you pressed on and inserted your off-topic plug.

 

[NTMBK]

There's a word called context that you should probably look up the definition of. Your comment was nonsensical given the preceding comments in the thread. In fact, Intel17 specifically mentioned that Nvidia was out of the smartphone game in his comment, yet you pressed on and inserted your off-topic plug.

The thread is about foundries and their customers, not mobile. Not sure why discussing NVidia's foundry partners is off topic

 

[Homeles]

The thread is about foundries and their customers, not mobile. Not sure why discussing NVidia's foundry partners is off topic

Follow the chain of comments?

 

[itsmydamnation]

Follow the chain of comments?

i did, seems to me, on one cared for your comment and was rather irrelevant within the context of the broader discussion that was being partaken within said thread........

 

[Homeles]

i did, seems to me, on one cared for your comment and was rather irrelevant within the context of the broader discussion that was being partaken within said thread........

Please refrain from commenting on my posts.

 

[NTMBK]

Please refrain from commenting on my posts.

But this whole conversation was triggered by you commenting on someone else's posts. Only seems fair to return the favour

Anyway, I followed the comment chain back as far as:

So who is still left in the big players in cellphones and laptops? Qualcomm, Intel, Marvel, Mediatek, who else?

Note the word "laptops". So even by your unconventional definition, his comment still wasn't "off topic". But I shall now stop going off topic.

 

[Homeles]

But this whole conversation was triggered by you commenting on someone else's posts. Only seems fair to return the favour

itsmydamnation and I have a bit of a history. He got upset at an argument I had with him over a year ago, and he's let that carry into every single discussion I've had with him on this forum, and elsewhere. It's really quite tiring.

Anyway, I followed the comment chain back as far as:

Note the word "laptops". So even by your unconventional definition, his comment still wasn't "off topic". But I shall now stop going off topic.

In the comment xpea was commenting on, Intel17 was talking about smartphones. I don't understand how so many people can't seem to figure this out, how this has dragged on so long, and why I'm suddenly the person under fire.

 

[NostaSeronx]

Samsung's 14-nm LPE/LPP is the equivalent to TSMC's 16-nm FF/FF+.

GlobalFoundries' 14-nm XM is the equivalent to TSMC's 16-nm FF.

Yeesh, that took me forever to find these.

14-nm XM ~=~ 16-nm FF ~=~ 14-nm LPE
14-nm FF+ ~=~ 14-nm LPP

(UTBB FDSOI destroys all of these statistically wise)

 

[mavere]

DigiTimes believes Samsung/GF's 14nm LPE won contracts from Qualcomm and Apple for their 2015 products. The article's sources then stated that TSMC's 16FF is an option for Apple's A9, while implying 16FF+ would be used for something else, if at all. (I was hoping for FF+/LPP for my potential iPhone 6s upgrade, but oh well)

There was also a mention of Intel as an option for A9-and-later SoCs, but those speculations have been around for so long that I'm just going to pretend they don't exist.

 

[ShintaiDK]

The PR is just crazy. So Samsungs 14nm FF offers even less than TSMCs 16nm FF and both are just a spinoff from the 20nm.

 

[Idontcare]

I'm not. IIRC, tape-outs, now-a-days, means a sample run in silicon. It used to just mean the design was ready to go to the fab (literally on mag-tape). So, GF could have pending orders waiting on a successful tapeout, but no hard orders yet if their process is still too immature. I'm just reaching for straws here - trying find out what is going on at Malta.

Tape-out still means what it always meant -> the design is complete and ready to be sent to the mask makers so the photo-masks can be made.

There is such a ridiculous amount of time still, and so many things that must be done to get the masks ready as well as the fab ready, before first silicon can actually sample in the fab on the tape-out design.

 

[Ajay]

Tape-out still means what it always meant -> the design is complete and ready to be sent to the mask makers so the photo-masks can be made.

There is such a ridiculous amount of time still, and so many things that must be done to get the masks ready as well as the fab ready, before first silicon can actually sample in the fab on the tape-out design.

Thanks for the explanation. I've seen the two merged in a couple of older PR pieces and thought the were being merged. I guess that was just a simplification for dumb end users like me

 

[witeken]

I was reading this presentation, and on page 7, it mentioned multiple transistor technologies like planar and FinFET.

There is an image of both FinFET and TriGate on SOI. The image of FinFET shows 2 gates, while Intel's TriGate shows 3 gates. Does this mean that Intel's 3D transistor solution is inherently superior to the foundries', and does this mean that TSMC's claim of 16FF+ being as good as Intel's 14nm is almost automatically false?

It's also interesting that this presentation, from 2011, mentions that they've grown III-V on bulk silicon. I know that Intel's been researching III-V since at least ~2008 or so, so I guess this refutes Imec's claim of "World’s First III-V FinFET" in September 2013 (the presentation says: 3D devices - partially done).

 

[mavere]

There is an image of both FinFET and TriGate on SOI. The image of FinFET shows 2 gates, while Intel's TriGate shows 3 gates. Does this mean that Intel's 3D transistor solution is inherently superior to the foundries', and does this mean that TSMC's claim of 16FF+ being as good as Intel's 14nm is almost automatically false?

You went from "3 > 2" to "Samsung/TSMC were built on lies; Intel is one true god" in a single breath...

At some point, enthusiasm starts sounding like parody.

 

[witeken]

You went from "3 > 2" to "Samsung/TSMC were built on lies; Intel is one true god" in a single breath...

At some point, enthusiasm starts sounding like parody.

OK, put another way: does TSMC's FF process have 2 or 3 gates and does it matter?

 

[Idontcare]

OK, put another way: does TSMC's FF process have 2 or 3 gates and does it matter?

3 gates. It does matter.

 

[witeken]

3 gates. It does matter.

Does that mean that Wikipedia is wrong? Could you elaborate on why 2 vs 3 gates matters and how much? How will GAA improve upon this?

 

[TuxDave]

Does that mean that Wikipedia is wrong?

On a personal level, I casually interchange tri-gates and finfets as they share the same general concept of a raised fin with a gate wrapped around it. Whether or not the top of the fin is an effective gate is an additional improvement on the idea. But yes, whether or not the raised fin is controlled by 2 gates or 3 gates makes a difference.

 

[witeken]

Which part of the Wikipedia article do you think is wrong?

"[...] to describe a nonplanar, double-gate transistor built on an SOI substrate"

But apparently it's now used for all 3D transistors.

Interesting edit.

 

[TuxDave]

Interesting edit.

Yeah I decided that I probably could spend the extra five minutes to read the article and link it back to the discussion vs punting the work back to you.

In the technical literature, FinFET is used somewhat generically to describe any fin-based, multigate transistor architecture regardless of number of gates

So yeah, basically the above (from the wikipedia article). Because of the casual usage of the word FinFET, you need to figure out if they're being technically precise or just using it as a casual term.