Samsung and GLOBALFOUNDRIES Forge Strategic Collaboration to Deliver 14nm FinFET

[Homeles]

Does that mean that Wikipedia is wrong? Could you elaborate on why 2 vs 3 gates matters and how much? How will GAA improve upon this?

AFAIK, a FinFET just describes a transistor device with a fin-shaped source and drain.

"[...] to describe a nonplanar, double-gate transistor built on an SOI substrate"

But apparently it's now used for all 3D transistors.

Interesting edit.

Not quite. 3D is a broader term. FinFET devices fall under 3D. GAA and Pi-Gate devices are also 3D.

 

[Ajay]

3 gates. It does matter.

IIRC, Intel uses 1, 2 and 3 fin xtors depending application (at least for Haswell).
That said, having the option to use up to 3 fins would seem to be an obvious advantage. Having the depth in your design team to take advantage of this is another issue, I suppose.

 

[TuxDave]

IIRC, Intel uses 1, 2 and 3 fin xtors depending application (at least for Haswell).
That said, having the option to use up to 3 fins would seem to be an obvious advantage. Having the depth in your design team to take advantage of this is another issue, I suppose.

Just a small point of clarification: # of fins is different than the # of effective gate sides per fin (which was asked).

Every company that uses finfets will find a need for multi-fin devices. In planar transistors, if you wanted to change drive strength, you had the design freedom to adjust the width of the gate and therefore allocate more room for the transistor in the planar direction. With fins, you really have only a couple ways to do it. Make each fin taller or fatter (to widen the channel and hence get more current) or add more parallel fins/transistors. Unless the process is so great that it can arbitrarily make any combination of fin heights and widths as the engineer pleased, you'll most often see multi-fin devices to generate different drive strengths.

 

[Homeles]

IIRC, Intel uses 1, 2 and 3 fin xtors depending application (at least for Haswell).
That said, having the option to use up to 3 fins would seem to be an obvious advantage. Having the depth in your design team to take advantage of this is another issue, I suppose.

Fin count is a separate parameter.

Whoops, Dave beat me to it.

1, 2, and 3 gate devices would have 3, 6, and 9 "effective" gates respectively.

This diagram should help:

Per transistor, there's one physical gate -- that remains unchanged, and undoubtedly is a great source of confusion. However each silicon channel is surrounded by the gate on 3 sides, and interacts with all 3 sides.

 

[Idontcare]

Yeah I decided that I probably could spend the extra five minutes to read the article and link it back to the discussion vs punting the work back to you.



So yeah, basically the above (from the wikipedia article). Because of the casual usage of the word FinFET, you need to figure out if they're being technically precise or just using it as a casual term.

The vernacular "FinFET" is meant to describe the topology of the channel, it is not meant to communicate the topology of gates.

For the most part this is true of all xtor descriptors.

"Planar CMOS" is meant to describe the shape of the channel as being 2D without telling you much about the gate arrangement. For example it is possible to have a so-called "double-gate" planar cmos xtor by way of creating a buried gate under the channel which is electrically connected to the same source and drain.

Same for FinFets, PiFets, Omega Fets, etc.

The argument (or purpose) for making a 2-gate FinFET versus a 3-gate FinFET is one of control and variability.

If you have good dimensional control, and low process variability (within die) then you want to take advantage of having that third-gate (the top gate) if possible.

If your process variability is to high, then it may actually be to your advantage to give up on trying to integrate a tri-gate finfet and just pursue doing a 2-gate finfet.

In Intel's case, they were able to drive their process development to an end result which enabled them to take advantage of the third gate without shooting themselves in the proverbial process-variability foot.

I am not aware of any company that is planning to put 2-gate finfets into production, they are all shooting for 3-gate finfet implementations.

Ultimately there can be 4-gate finfets (so-called 'all-around gate FinFet') if a bottom gate were to be integrated under the fin at some point.

 

[jdubs03]

@idc Nice explanation.

I have seen research on two-gate transistors both 2D and 3D; MuGFETs. A gate-all-around structure provides the highest drive current, and like you said better control; so it would seem to me that because of GAA being related to Tri-Gate FInFETs, an all around implementation (nanowires) make it the forerunner for next-Gen 7nm transistor structure, TFETs IMO have a slimmer chance (both being III-V materials).

 

[Ajay]

That worked out well - some great information because I mis-read 'gates' as fins :whiste:

 

[Phynaz]

The vernacular "FinFET" is meant to describe the topology of the channel, it is not meant to communicate the topology of gates.

For the most part this is true of all xtor descriptors.

"Planar CMOS" is meant to describe the shape of the channel as being 2D without telling you much about the gate arrangement. For example it is possible to have a so-called "double-gate" planar cmos xtor by way of creating a buried gate under the channel which is electrically connected to the same source and drain.

Same for FinFets, PiFets, Omega Fets, etc.

The argument (or purpose) for making a 2-gate FinFET versus a 3-gate FinFET is one of control and variability.

If you have good dimensional control, and low process variability (within die) then you want to take advantage of having that third-gate (the top gate) if possible.

If your process variability is to high, then it may actually be to your advantage to give up on trying to integrate a tri-gate finfet and just pursue doing a 2-gate finfet.

In Intel's case, they were able to drive their process development to an end result which enabled them to take advantage of the third gate without shooting themselves in the proverbial process-variability foot.

I am not aware of any company that is planning to put 2-gate finfets into production, they are all shooting for 3-gate finfet implementations.

Ultimately there can be 4-gate finfets (so-called 'all-around gate FinFet') if a bottom gate were to be integrated under the fin at some point.

Zoom...most of this went right over my head.

But I have a question what this means for process engineers like yourself. Does the planar skill set still apply, or are those guys obsolete? When Disney switched to all digital animation they closed their hand animation studios and laid off all the old school hand animators. Will / is the same thing happening to planar engineers?

 

[Ajay]

I have seen research on two-gate transistors both 2D and 3D; MuGFETs. A gate-all-around structure provides the highest drive current, and like you said better control; so it would seem to me that because of GAA being related to Tri-Gate FInFETs, an all around implementation (nanowires) make it the forerunner for next-Gen 7nm transistor structure, TFETs IMO have a slimmer chance (both being III-V materials).

While I think you are correct, there is ongoing research into TFETs that is showing promise: http://phys.org/news/2013-08-tunnel-fet-architecture-potential-substantial.html.

Traditional TFETs deliver an Idrive much lower than MOSFET and more quickly become insensitive to increases Vgate resulting in a low sub-threshold swing (SS) - so I thought TFET would be a tough sell. These SE-TFETs have a much steeper SS than MOSFET, and at least in this study, produce an equivalent Idrive at much lower voltages. It's pretty much the adoption of a "Fin" style gate to a traditional planar TFET (which doesn't look like an extreme challenge in terms of manufacturability).

There's nothing here about switching speed or scale-ability, but long-term this seems like a promising path worth pursuing. Of course, as with the case of NAND, going 3D may prove to be a more cost effective method of increase xtor density - it's just seems to be more challenging to do with logic vs. the more regularly patterned layout of solid state memory.

 

[Idontcare]

Zoom...most of this went right over my head.

But I have a question what this means for process engineers like yourself. Does the planar skill set still apply, or are those guys obsolete? When Disney switched to all digital animation they closed their hand animation studios and laid off all the old school hand animators. Will / is the same thing happening to planar engineers?

Interestingly enough the skill sets (experience) translate in nearly 1:1 fashion. Folks with 20+ yrs of planar CMOS process experience have no problem stepping into the non-planar realm and advancing the state-of-the-art from day 1 no less than the guy who just walked off a college campus with a shiny new PhD.

Where the wheels fall off the wagon for the planar-experienced folks is when it comes to new materials (regardless of the topology for which they are being employed). HKMG is a perfect recent example. It completely hosed up process engineers who simply did not have a firm basic understanding of rudimentary materials science and chemistry.

So that is the gap, and the opportunity, right now in semiconductors between the experienced hands and the new salts.

The new salts benefit from their recent uni chem classes and materials science courses in having the advantage of knowing of the latest understandings in organo-metallic chemical reaction theory and so forth. All the stuff you need to be innovative in the trenches whilst working on rapidly evolving (node to node) material compositions and film types.

The old hands are behind the curve there, not having stepped inside a college classroom in say 20 yrs perhaps, and are doing what they can to make 21st century transistors with their circa 1990's science education.

But that is only an issue for old hands that did not have a strong grasp of chemistry and materials science in the first place, or who lost the passion and interest to learn more by staying up on things in technical journal publications (academic ones, not trade journals from the industry which tend to be light on science and long on IP protection).

A personal example where I got my own wake-up call that I was coasting far too long on my (then becoming dated) education was with FeRam. I was asked to step in and assist a development team on particle reduction efforts and without thinking too much about the materials involved (I was coasting, auto-pilot thinking, a lot of 'rinse and repeat' type experiments) I exposed the PZT material in the FeRAM to a liquid chemistry that created an awesome galvanic battery cell and resulted in spectacular corrosion to the wafers.

That misstep woke me up and changed my approach to how I was refreshing my aging academic knowledge base. The change in approach has served me well ever since, and I came to recognize it in my peers who had experienced similar wake-up calls as well.

So I believe that group of old hands will do fine as the materials landscape, and xtor topology, evolves and morphs in time. But it is the group of folks who can't pull themselves out of that coasting mentality, relying on an out-dated sense of what they had been taught of chemistry in the 70's or 80's while trying to apply it to the quantum chemistry world of nanometer thick films of novel material compositions that are in for a rough transition in their career path.

 

[AtenRa]

I exposed the PZT material in the FeRAM to a liquid chemistry that created Galvatron and resulted in spectacular Transformers 4.

Good to now it was you that created Galvatron after all

Sorry IDC i couldn't resist

 

[Idontcare]

Good to now it was you that created Galvatron after all

Sorry IDC i couldn't resist

that was good!

Unfortunately it is true, the NSA knows who you are and where you are, and a helpful team of cleaners have been dispatched to assist in seeing that err is rectified

All hail Gallaxhar!

 

[witeken]

Most foundries have yet to start buying the capital equipment needed for the 14/16 nm node, which for many will be the first to support FinFETs, says Trafas of KLA-Tencor. Gear companies hope the orders start coming in the fall.

While I was reading this article from Russ Fischer, he quoted this from an article. He said this implies there will be no FinFETs in 2015. What do you think? I guess this in any case means no HVM in 2014 so he's correct, although that's not a big surprise since Qualcomm will only have 20nm SoCs in 2015.

 

[witeken]

Also, this article isn't optimistic about the future foundry nodes either.

Handel said “there is a significant challenge in getting lower cost at 20nm” compared to 28nm due to a lack of increase in the gate density and the potential yield impact. “We think 20nm, if it does go into volume production, it will not be in 2014. Potentially 2015 and maybe 2016,” he said.

Similarly, Handel believes there will be a postponement of 16/14nm. “We expect initial production in late 2016, beginning of 2017. That’s for the SoC business. The FPGA markets will be different,” he said. “There will also be delays in 10nm. Delays mean you can’t really go on the 2 year cycle or even the 3 year. I know people will vehemently disagree with that, but if you look at what’s really happening from a design start point of view and also the end customers, I think you’ll agree with our conclusion,” he said.

Not surprisingly, Handel also had a dim outlook for 10nm. He estimates that 10,000 wafers/month at 10nm will cost more than $2billion. “If you want to install 40,000 wafers/month, it’s going to be an $8 billion bill. If you want to install 100,000 wafers/month, it’s going to be $20 billion. Even before you get to 450mm, it’s going to be significantly more capital intensive,” he said.

Handel said the gate utilization is an issue because of limitations of the design tools and parasitic effects. “The other factor is parametric yields, which are strictly tied into leakage control for the 20nm and of course for the 16nm FinFETs,” he said. “You can break this. Intel has shown that it can be broken and of course that’s an excellent achievement. But, it’s based on very high design costs, potentially $1 billion per design, so you need $10 billion in revenue. It also takes a number of years,” he said. He noted that, in the smartphone market, designs move very fast. “You can’t make that kind of investments in designs.”

 

[jdubs03]

While I was reading this article from Russ Fischer, he quoted this from an article. He said this implies there will be no FinFETs in 2015. What do you think? I guess this in any case means no HVM in 2014 so he's correct, although that's not a big surprise since Qualcomm will only have 20nm SoCs in 2015.

i don't know how he be legitimately say that when it's been quoted by corporate executives and industry folk. TSMC says HVM for 2H2015, and Samsung/GLF at the same time or a little before (as allegedly they're beating TSMC to shipments).

we'll see in september when apple announces the iphone 6, that will give us a better idea.

 

[witeken]

i don't know how he be legitimately say that when it's been quoted by corporate executives and industry folk. TSMC says HVM for 2H2015, and Samsung/GLF at the same time or a little before (as allegedly they're beating TSMC to shipments).

we'll see in september when apple announces the iphone 6, that will give us a better idea.

He says:

"If the equipment orders are not even placed yet, we can kiss off 2015 delivery, regardless of what the PowerPoint presentations say."

 

[mavere]

TSMC last week claimed they will get single digit percentage 14/16FF revenue in Q4'15. They also admitted that a historical competitor foundry will temporarily get more 14/16nm business in late '15, which is an odd admission in an investor conference call unless the lost business will cause too much movement to be unnoticed (*cough* Apple), and TSMC thinks it's impossible to equivocate about the competition not meeting their timetables.

Meanwhile, in April, BNP Parisbas stated in a research report, that Samsung should be able to ramp up to 40k wpm 14/16FF output in Q4'15.

 

[Fjodor2001]

So when will we see TSMC/Samsung 14 nm in actual products that are available in the shops?

 

[Ajay]

So when will we see TSMC/Samsung 14 nm in actual products that are available in the shops?

HVM will have to be late 2016 early 2017. Risk production will be earlier (lower clocked, less complex ASICs) from from test lines. In Mr. Handel's comments - I don't think he's saying _no_ equipment has been purchased, just no high volume purchases.

I think this is being driven by customers; who just cannot afford 20nm yet, let alone 14/16FF. From the article, there are only two key companies driving production:

Perhaps most surprisingly, he had a fair amount of uncertainly about 20nm. “Will 20nm be a high tech technology node and when will that occur?” he said. “We’re tracking design starts and design completions and we see a few 20nm designs but not a lot. Frankly, whether 20nm will be big or not will really depend on two customers: one is Qualcomm and the other is Apple.” Handel said “there is a significant challenge in getting lower cost at 20nm” compared to 28nm due to a lack of increase in the gate density and the potential yield impact. “We think 20nm, if it does go into volume production, it will not be in 2014. Potentially 2015 and maybe 2016,” he said.

.

Everyone else (aside from Intel) is dependent on these two companies pushing the envelope and driving enough volume over time to decrease the ASP on wafers.


PS Thanks witeken for digging up this info - very informative!

 

[mavere]

So when will we see TSMC/Samsung 14 nm in actual products that are available in the shops?

Probably a late 2015 Apple A9 SoC on Samsung's 14LPE. I can't think of anything else with enough volume to cause TSMC to admit (temporary) defeat to investors.

Oh, and I forgot to link the TSMC's conference call transcript earlier.

 

[Fjodor2001]

Hmm... Ajay says 2016/2017, mavere 2015. That's quite a big difference.

If it's 2015 then TSMC/Samsung will be around 1 year behind Intel on 14 nm, assuming Intel will release 14 nm in late 2014Q4 or 2015Q1 as expected.

 

[Ajay]

Probably a late 2015 Apple A9 SoC on Samsung's 14LPE. I can't think of anything else with enough volume to cause TSMC to admit (temporary) defeat to investors.

Good point. Sammy's 14nm is supposedly the class of the field right now and ahead of every other foundry in TTM. I imagine Qualcomm will follow. I wonder if they will go for Samsung 14FF (@GF maybe?) or 16FF @ TSMC?

This is bad for dGPU, apparently, they just don't have the $$ volume to enter into these new nodes in their first year (or maybe two with FinFets).

 

[Ajay]

Hmm... Ajay says 2016/2017, mavere 2015. That's quite a big difference.

If it's 2015 then TSMC/Samsung will be around 1 year behind Intel on 14 nm, assuming Intel will release 14 nm in late 2014Q4 or 2015Q1 as expected.

I glossed over mavere's comments too quickly (and the very detailed report from BNP Parisbas that he linked - that I'm not done with). Having and 'wealthy' customer waiting on Samsung's production changes things quick a bit.

Again, in the past we had a situation where more IDMs could afford the foundry's bleeding edge node (like AMD and Nvidia for dGPUs). In the current climate, customer design time and fab wafer costs are become much more significant limiting factors regarding the adoption of new process tech).

 

[Fjodor2001]

I glossed over mavere's comments too quickly (and the very detailed report from BNP Parisbas that he linked - that I'm not done with). Having and 'wealthy' customer waiting on Samsung's production changes things quick a bit.

Again, in the past we had a situation where more IDMs could afford the foundry's bleeding edge node (like AMD and Nvidia for dGPUs). In the current climate, customer design time and fab wafer costs are become much more significant limiting factors regarding the adoption of new process tech).

Ok, so assuming Apple makes Samsung/GF push out 14 nm in 2015, when can we expect AMD to get access to 14 nm? Early 2016?

 

[Ajay]

Ok, so assuming Apple makes Samsung/GF push out 14 nm in 2015, when can we expect AMD to get access to 14 nm? Early 2016?

One, Apple isn't so much pushing Samsung - Samsung upped it's game and had a process ready that Apple bought into, which means Samsung will be able to move forward with production.

Second, last we heard Samsung was dragging it's feet on helping GF. This is probably so that they can get the lion share of Apple SoC orders - at least initially. Now, Apple could hold Samsung's feet closer to the fire and get them moving on helping GF (since they want a second source) - but even Apple knows Samsung needs to hit a certain RIO. So, this is just a guess here, but I expect GF to be ~6-9 months behind Samsung - it depends somewhat on how much GF is paying Samsung for the their IP and implementation.

The big question for GF, is when will other customers bite on 14FF - picking up some of Qualcomm's business is possible, if the cost will be better than TSMC's around the same time frame.