Kepler vs Fermi is irrelevant. We know per EU performance will be better with Gen8(Due to Broadwell GT SKUs). And we know Gen8 devices contains more EUs. Specially Cherrytrail with 4x the EUs over Baytrail.
As i have explained earlier with Kepler and Fermi Architectures, we shouldn't compare number of EUs between different Architectures. It may well be that Intel Gen 8 EUs have lower performance each (smaller size) than Gen 7/7.5 in order to raise throughput (more units in the same space).
Kepler vs Fermi is irrelevant. We know per EU performance will be better with Gen8(Due to Broadwell GT SKUs). And we know Gen8 devices contains more EUs. Specially Cherrytrail with 4x the EUs over Baytrail.
We have performance data from Broadwell iGPU today ???
Lots of PhDs went into designing Netburst, too.
In my mind, Netburst, much as it's maligned, brought some very good things internally for Intel design teams. First, unbelievable circuit expertise (the FP logic was running at 8GHz in Prescott stock!). Next, the trace cache which you can see reimplemented in Sandy and Ivy Bridge. Also, SMT. Building a validation team that could validate the beast pre- and post-silicon. The power-perf thinking i.e. frequency through power savings. Finally, the development of tools and project management required to do that kind of extreme design. All of these learning continue to this day and it's a very large contributor to why in client and server CPUs Intel can sustain the roadmap we have.
We know the EU number for the same GT SKU is increased with 20%.
Larrabee is another good example of that.Yup, that Netburst. Even a failed project can still produce plenty of useful knowledge and expertise.
So when Intel says Broadwell graphics bring some of the biggest changes weve seen on the execution and memory management side of the GPU [the changes] dwarf any other silicon iteration during my tenure, and certainly can compete with the likes of the gen3->gen4 changes., then to me that means we should expect a big improvement. That's what Occam's Razor tells us to expect and it's far more sensible than this conspiracy theory.
So what are the odds of seeing a 20nm FD SOI to improve performance without the added cost of finfets?
Obviously large scale product says the SOI costs more for SIO wafers, but it might be cheaper than finfets, plus high yields if SOI marketing is actually true. Plus it would be good for mobile battery life, even if it costs more the margins will be there to recoup the added cost
So what are the odds of seeing a 20nm FD SOI to improve performance without the added cost of finfets?
Obviously large scale product says the SOI costs more for SIO wafers, but it might be cheaper than finfets, plus high yields if SOI marketing is actually true. Plus it would be good for mobile battery life, even if it costs more the margins will be there to recoup the added cost
Fortunately, FD-SOI is all that, and that is the reason it is getting widely adopted by everyone. STMicroelectronics, IBM, GlobalFoundries, Samsung, etc, are all adopting FD-SOI for HVM.
FD-SOI delivered and all devices on FD-SOI will clearly be Faster, Cooler, Simpler than their bulk FinFET counterparts. The smart-money business is clearly opting for FD-SOI. Which implies the actual FD-SOI product is over and beyond promised targets.
The best part of FD-SOI is that it will always be compatible with SOI FinFETs. Hybrid FinFET/Planar at the 10-nm node, will insure that the best fin or planar gate is used for "X" device.
Fortunately, FD-SOI is all that, and that is the reason it is getting widely adopted by everyone. STMicroelectronics, IBM, GlobalFoundries, Samsung, etc, are all adopting FD-SOI for HVM.
FD-SOI delivered and all devices on FD-SOI will clearly be Faster, Cooler, Simpler than their bulk FinFET counterparts. The smart-money business is clearly opting for FD-SOI. Which implies the actual FD-SOI product is over and beyond promised targets.
The best part of FD-SOI is that it will always be compatible with SOI FinFETs. Hybrid FinFET/Planar at the 10-nm node, will insure that the best fin or planar gate is used for "X" device.
Unfourtunately not - both GF\Samsung have rejected FDSOI as viable - and ibm becoming fringe if even existing fab at all in the next few years - it has zero adoption.
Unfourtunately not - both GF\Samsung have rejected FDSOI as viable - and ibm becoming fringe if even existing fab at all in the next few years - it has zero adoption.
From what I know according to the SOI consortium, SOI FinFET's offer the best perf/cost, but if that were the case we should have already heard about implementation of this on the next nodes, I haven't seen that aside from STMicro, and IBM for the most part.
IBM is selling its foundry business and STM is largely irrelevant in the big picture. Nobody relevant is still with SOI.
Apart from Samsung, as pointed out in the post immediately above you.
I don't want to start a new thread...
Samsung LPE and LPP have disappeared in the latest roadmaps.
GlobalFoundries is doing some weird stuff... which constantly conflicts with stuff. (The latest one still under restrictive access shows 20FD/'14FD' below 10XM.)
If you guys don't know what I'm talking about; "Samsung LPE and LPP have disappeared in the latest roadmaps."
It is like there is two different people making these roadmaps. Which are constantly fighting who is right and who is wrong. Get your act together GlobalFoundries, yeesh.
GlobalFoundries can most likely supply these nodes. It is just no one wants to pay for 0% yields.Doing public advertisement of product you cant supply is illegal.
GlobalFoundries can most likely supply these nodes. It is just no one wants to pay for 0% yields.