Samsung Claims Mass Production on 14-Nanometers

[witeken]

really interesting though that intel didnt spend any time talking about their foundry strategy during the analyst day. the tool hookup contractor i talked to that had worked in austin was actually working in israel standing up inte's 10nm facility in kiryat. he made some comments with regard to their fab structures not really being designed to do general purpose foundry. i need to further dig into this. He was speculating 10nm in Chandler could be stood up for Apple in the future but that was pure hypothesizing.

Intel talked about their 14nm foundry last year at IM (they have a lot more process flavors than just a few years ago). They now reiterated their 5 customers. Their strategy is that they are willing to talk to everyone who is interested, but will only accepts if it makes (economical) sense. Not sure what else you want to know.

 

[liahos1]

Intel talked about their 14nm foundry last year at IM (they have a lot more process flavors than just a few years ago). They now reiterated their 5 customers. Their strategy is that they are willing to talk to everyone who is interested, but will only accepts if it makes (economical) sense. Not sure what else you want to know.

dunno but they barely mentioned it at the investor meeting this year. it doesnt really seem like its a going anywhere other than the small fpga guys, altera and panasonic. if apple is willing to pay higher $/transistor at 20nm why wouldnt they take pay that premium for 14nm capacity from intel.

 

[witeken]

Sure, not all 14 nm are created equal. Nobody's arguing about that. One may be better than the competition in one aspect, and worse in another.

But do you really have the metrics data to show that Intel 14 nm is better than Samsung 14 nm in every aspect? If so, then please share it with us. I'm talking about transistor density, power consumption, price per transistor, max performance, yield, etc.

And are the differences really big enough to matter?

Density: http://forums.anandtech.com/showthread.php?p=36610921#post36610921

Samsung 14nm - 78nm*64nm = 4992
Intel 14nm - 70nm*52nm = 3640

Performance and power: Intel's better because they're in their 2nd generation. See my signature. Yield: although yield figures are obviously not available, Intel has a stellar reputation, as far as I know. I've seen (that was a year ago, so I won't be able to find it) a response on SeekingAlpha from someone who worked a both Intel and TSMC, and apparently he had some insight: he basically said Intel was vastly superior to TSMC's yield learning. For max performance you also look at Intel's products (performance is also determined by the design): 22nm can go up to 5GHz, and there's no reason 14nm would clock lower.

Price per transistor: is a function of density, yield and wafer cost.

 

[Gikaseixas]

I knew i would find people defending Intel. Density is not, i repeat, is not the only conditional for a 14nm quality product. Stop defending a product no one has tested. I'm not saying SS has nailed it and will destroy Intel but to go ahead and say Intel is better without even seeing it out there....

 

[kimmel]

I knew i would find people defending Intel. Density is not, i repeat, is not the only conditional for a 14nm quality product. Stop defending a product no one has tested. I'm not saying SS has nailed it and will destroy Intel but to go ahead and say Intel is better without even seeing it out there....

I knew people would be saying that Samsung has caught up to Intel and will soon surpass them without a single product available for a third party such as Chipworks to dissect.

 

[krumme]

http://www.strategyand.pwc.com/glob...lobal-innovation-1000/top-20-rd-spenders-2013

Thanx. Its difficult to assess whats going into micrprocessor vs eg oled. But its a dramatic increase non the less.
A second factor is the consolidation of process tech is accelerating like crazy. We migh have several foundry players but effectively only 2 high end process development globally with tsmc lagging ss. All happening next to the arm ecosystem. With apple as the boss. Its a huge force combined.
Its about time something happened.

 

[Hans de Vries]

Density: http://forums.anandtech.com/showthread.php?p=36610921#post36610921

TSMC 20nm - 90nm*64nm = 5760
Samsung 14nm - 78nm*64nm = 4992
Intel 14nm - 70nm*52nm = 3640

By this metric that Intel clearly defined, Intel meets the claims that it set out previously. Whether this is the best measure, that's up to the viewer.

Realize that:

1) Intel uses 1D interconnect versus TsMC/Samsung/GloFo/UMC who
all use 2D interconnect.

2) These cell dimensions provide a theoretical maximum density which
only can be achieved with perfect interconnection between the cells.

In real life Logic circuits this maximum is never reached. Far from:

The average transistor in Core M takes about (82e12/1.3e9) =
63079 nm^2 which is 17.5 times the minimum FinFet cell size of
3600 nm^2

Intel's 2.2x density increase comes more from going from 9 to 13
interconnect layers, and I expect even more layers in their 10nm
process (16?)

source

2D interconnect provides a higher density with the same number
of interconnect layers, or the same density with less interconnect
layers.

Apples A8x has an average transistor size of (125e12/3e9) =
41666 nm^2, also much higher as the minimum FET cell size of
5760 nm^2, but the utilization is higher due to the 2D interconnect
and the number of high density interconnect layers.

 

[Gikaseixas]

I knew people would be saying that Samsung has caught up to Intel and will soon surpass them without a single product available for a third party such as Chipworks to dissect.

This doesn't validate what Intel fanboys spread out there does it? I said in my post that saying SS finally caught Intel was wrong too, both sides are wrong to play "Nostradamus" so why did you feel compelled to come to Intel's defense??? I know why but anyway

 

[witeken]

I knew i would find people defending Intel. Density is not, i repeat, is not the only conditional for a 14nm quality product. Stop defending a product no one has tested. I'm not saying SS has nailed it and will destroy Intel but to go ahead and say Intel is better without even seeing it out there....

You haven't seen the Yoga 3 Pro review, have you? A sub 4W device that is vastly superior to any ARM SoC you throw at it and is able to stay only relatively close behind 22nm 15W SoCs. The people from Chipsworks have already taken their first look at 14nm and will soon confirm the rectangular transistors and air gaps.

 

[Gikaseixas]

A sub 4W device that is vastly superior to any ARM SoC

So by embarrassing existing tech makes it better than similar tech (14nm) that is not released yet??? WOW

None of us know
Who here knew Athlon would be better than P4 with HT? Who knew Core would demolish X2's?

 

[oobydoobydoo]

It's Exynos.

Exynos 5433 20nm still isn't available in a phone IIRC so it would be surprising to see 14nm in April with the release of the S6, but perhaps Samsung sees the benefits Apple is currently getting with 20nm A8/X. I still would place my bets that Apple is sourcing A9 from Samsung/GloFlo, they are the big dog now in ARM. $700 billion valuation today.

 

[witeken]

Realize that:

1) Intel uses 1D interconnect versus TsMC/Samsung/GloFo/UMC who
all use 2D interconnect.

I didn't realize that. What is the difference?

In real life Logic circuits this maximum is never reached. Far from:

The average transistor in Core M takes about (82e12/1.3e9) =
63079 nm^2 which is 17.5 times the minimum FinFet cell size of
3600 nm^2

Why is that?

Intel's 2.2x density increase comes more from going from 9 to 13
interconnect layers, and I expect even more layers in their 10nm
process (16?)

It also comes from lower variation resulting in less fins necessary and of course the decreased features sizes. BTW, Haswell had 11 interconnect layers IIRC.

Apples A8x has an average transistor size of (125e12/3e9) =
41666 nm^2, also much higher as the minimum FET cell size of
5760 nm^2, but the utilization is higher due to the 2D interconnect
and the number of high density interconnect layers.

I don't think Intel used the highest density process for Core M. Cherry Trail's density should be higher.

 

[Arachnotronic]

Realize that:

1) Intel uses 1D interconnect versus TsMC/Samsung/GloFo/UMC who
all use 2D interconnect.

2) These cell dimensions provide a theoretical maximum density which
only can be achieved with perfect interconnection between the cells.

In real life Logic circuits this maximum is never reached. Far from:

The average transistor in Core M takes about (82e12/1.3e9) =
63079 nm^2 which is 17.5 times the minimum FinFet cell size of
3600 nm^2

Intel's 2.2x density increase comes more from going from 9 to 13
interconnect layers, and I expect even more layers in their 10nm
process (16?)

source

2D interconnect provides a higher density with the same number
of interconnect layers, or the same density with less interconnect
layers.

Apples A8x has an average transistor size of (125e12/3e9) =
41666 nm^2, also much higher as the minimum FET cell size of
5760 nm^2, but the utilization is higher due to the 2D interconnect
and the number of high density interconnect layers.

Intel moved to 11 interconnect layers for Haswell. Ivy Bridge was 9.

Also keep in mind that the SoC processes from Intel are typically denser than the high perf. CPU processes.

For example, Medfield on 32nm packed 432m transistors in a 64mm^2 area, or about 6.75 million transistors per mm^2. Intel Sandy Bridge, also 32nm, packed 1.16 billion transistors into 216mm^2, or density of "just" 5.37 million transistors per mm^2.

I'd be willing to bet that Cherry Trail is significantly denser than Core M.

 

[Hans de Vries]

I'd be willing to bet that Cherry Trail is significantly denser than Core M.

I would think so too.

Hans

 

[Skurge]

Exynos 5433 20nm still isn't available in a phone IIRC so it would be surprising to see 14nm in April with the release of the S6, but perhaps Samsung sees the benefits Apple is currently getting with 20nm A8/X. I still would place my bets that Apple is sourcing A9 from Samsung/GloFlo, they are the big dog now in ARM. $700 billion valuation today.

International Galaxy Note 4 uses 20nm Exynos 5433. Galaxy Alpha uses 20nm Exynos 5430.

 

[Fjodor2001]

What on Earth?!

Read the parts of my post that you did not quote for an explanation. The point is that Intel's process lead is shrinking and is now effectively down to 2-3Q on 14 nm. So if that trend continues then Intel will eventually be surpassed.

 

[witeken]

Read the parts of my post that you did not quote for an explanation. The point is that Intel's process lead is shrinking and is now effectively down to 2-3Q on 14 nm. So if that trend continues then Intel will eventually be surpassed.

So what is TSMC's or Samsung's 22nm equivalant?

 

[Hans de Vries]

I didn't realize that. What is the difference?

1D patterns have only horizontal lines or only vertical lines on a
single interconnect layer. Therefor they can be made easier with
multi-patterning methods. First the lines are made (like in the middle
image) and secondly the lines are cut into smaller pieces.

2D interconnect has a combination of horizontal and vertical lines on
each interconnect layer. It's much harder to make them with multi-
pattern methods and they need complex color schemes like the one
below.

Why is that?

In regular structures like memories you can layout these cells side-by-side
but in general logic circuits (which are also called 'random' logic circuits,
because they do not have a regular structure) that's not possible because
of the 'spaghetti wiring' between the cells. The wires take much more
space as the transistors.

I don't think Intel used the highest density process for Core M. Cherry Trail's density should be higher.

You are most probably right. They have shown different interconnect
structures for different targets.

 

[Hans de Vries]

http://s3.mentor.com/ic/Foundry-Double-Patterning-Exposed.pdf

Lots of links here to the autor's multi-patterning articles.

 

[NostaSeronx]

GloFo/Samsung;
48-nm Fin Pitch
78-nm Gate Pitch
64-nm 2D Interconnect Pitch
0.064μm² HD SRAM

TSMC;
48-nm Fin Pitch
90-nm Gate Pitch
64-nm 1D Interconnect Pitch
0.07µm² HD SRAM

Intel;
42-nm Fin Pitch
70-nm Gate Pitch
52-nm 1D Interconnect Pitch
0.0588μm² HD SRAM

TSMC is 1D.

 

[III-V]

Read the parts of my post that you did not quote for an explanation. The point is that Intel's process lead is shrinking and is now effectively down to 2-3Q on 14 nm. So if that trend continues then Intel will eventually be surpassed.

How in the world did you manage to come to this conclusion, when all facts point to the opposite trend? It's like this with you and nearly every other subject you talk about as well.

 

[Fjodor2001]

How in the world did you manage to come to this conclusion, when all facts point to the opposite trend? It's like this with you and nearly every other subject you talk about as well.

As I said, read the post I referred to and you'll find what you're looking for. Also, please drop your usual insults.

 

[carop]

GloFo/Samsung;
48-nm Fin Pitch
78-nm Gate Pitch
64-nm 2D Interconnect Pitch
0.064μm² HD SRAM

TSMC;
48-nm Fin Pitch
90-nm Gate Pitch
64-nm 1D Interconnect Pitch
0.07µm² HD SRAM

Intel;
42-nm Fin Pitch
70-nm Gate Pitch
52-nm 1D Interconnect Pitch
0.0588μm² HD SRAM

TSMC is 1D.

The Intel high density SRAM cell size should be 0.050 μm2. This will be presented at ISSCC in February 2015. The high density cell uses one-fin for pull-down NMOS sizing.

The 0.058 μm2 is the cell size of what Intel calls the low voltage cell. The low voltage cell uses two-fins for pull-down NMOS sizing. You can see the pull down fins in the very blurry SEM image published by Intel.

Are you sure TSMC M1 is 1D?

 

[Fjodor2001]

So what is TSMC's or Samsung's 22nm equivalant?

Exactly. On 22 nm Intel had a larger process tech lead than on 14 nm. Hence their lead is shrinking.

 

[Phynaz]

How in the world did you manage to come to this conclusion, when all facts point to the opposite trend? It's like this with you and nearly every other subject you talk about as well.

Intel haters will naturally spin things to make Intel be shown in the worst possible light.