Samsung to build 14nm chips next year

[AtenRa]

It's not necessary to provide sources for common knowledge.

Intel has had substantial performance leads over its competition for well over a decade. It is you that needs to provide evidence disputing the contrary.

But here, I'll help us both out:
http://www.realworldtech.com/includes/images/articles/iedm10-10.png?71da3d

On every comparison point that exists, TSMC et al. lose out considerably.

First of all the link you provided doesnt have Intels 22nm FF or TSMC 20nm Planar.

Secondly, i have already provided Metal Pitch numbers for both process that shows TSMC 20nm Metal Pitch(64nm) to be superior against Intels 22nm FF(90nm).

Lets see SRAM Cell size,

Intel 22nm FF = 0.092μm2

TSMC 20nm Planar = 0.081μm2

Almost 12% smaller

Thirdly, nobody have provided any other numbers to support witeken suggestion of Intels 22nm FF being vastly superior to TSMCs 20nm Planar. But according to Metal Pitch and SRAM Cell size, it is TSMCs 20nm process that is superior to Intels 22nm FF making witeken claims incorrect.

If you or others have electrical characteristics of both 20nm and 22nmFF to compare, by all means please post them so we can see which one is the better process.

Until then, TSMCs 20nm is better due to smaller Metal Pitch and SRAM Cell size.

 

[NTMBK]

And when they do go FinFET it'll be with Globalfoundries, not Samsung.

GloFo are licensing Samsung's 14nm process. AMD will be able to dual source.

 

[witeken]

For density, yes -- there's no arguing that. But for performance, no. Intel's lag in density is equally met by their competitor's lag in performance. With 14nm, for the first time, Intel will have a lead in both density and performance, and it's very probable this will be true for 10nm as well, although it's too early to say for certain.

All those node comparisons are all fine and such, but what I'm really interested in is seeing how this translates to a TTM graph; it doesn't matter if 22 has worse characteristics than 20, because they'll never be competitors.

One could argue that TSMC still has better density than Intel's 14nm, if they hadn't done that 20->16 step without density changes; TSMC 10 vs Intel 14.

 

[NostaSeronx]

Intel 22nm FF = 0.092μm2

TSMC 20nm Planar = 0.081μm2

Doing comparisons like this is irrelevant.

High Density 6T SRAMs @ TSMC do not equal High Density 6T SRAMs @ Intel. High density has its own definition at each individual foundry.

TSMC 10 vs Intel 14.

TSMC's 10-nm node will be more dense than Intel's 10-nm node. For one big reason that is called EUV.

 

[AtenRa]

GloFo are licensing Samsung's 14nm process. AMD will be able to dual source.

Well, actually everyone should be able to dual source, that was the idea in the first place.

 

[Homeles]

First of all the link you provided doesnt have Intels 22nm FF or TSMC 20nm Planar.

Secondly, i have already provided Metal Pitch numbers for both process that shows TSMC 20nm Metal Pitch(64nm) to be superior against Intels 22nm FF(90nm).

Lets see SRAM Cell size,

Intel 22nm FF = 0.092μm2

TSMC 20nm Planar = 0.081μm2

Almost 12% smaller

Thirdly, nobody have provided any other numbers to support witeken suggestion of Intels 22nm FF being vastly superior to TSMCs 20nm Planar. But according to Metal Pitch and SRAM Cell size, it is TSMCs 20nm process that is superior to Intels 22nm FF making witeken claims incorrect.

If you or others have electrical characteristics of both 20nm and 22nmFF to compare, by all means please post them so we can see which one is the better process.

Until then, TSMCs 20nm is better due to smaller Metal Pitch and SRAM Cell size.

You are seriously in denial. Intel's had a substantial performance lead for well over a decade, and perhaps forever, and you think that this somehow has changed?

Learn to extrapolate.

Anyway, as far as Intel 22nm goes, Intel achieves 410 ua/um Ion with 0.003 na/um Ioff @ 0.075V for their 22nm LP process for NMOS. TSMC achieves 700 ua/um Ion with 100 na/um Ioff @ 0.08V. That's... nearly 3 orders of magnitude higher leakage than Intel.

At .8V, at the same 100 na/um leakage, Intel would get well over 1200 ua/um.. but of course it doesn't scale that high.

 

[lefty2]

GloFo are licensing Samsung's 14nm process. AMD will be able to dual source.

That's irrelevant. AMD have a contract with Globalfoundries, not Samsung.

 

[AtenRa]

You are seriously in denial. Intel's had a substantial performance lead for well over a decade, and perhaps forever, and you think that this somehow has changed?

Learn to extrapolate.

Im the one that has provided numbers to show 20nm being better than 22nmFF and im the one in denial ???

Even if Intels 22nmFF has better electrical characteristics than TSMCs 20nm planar that doesnt make 22nm FF Vastly superior because 20nm has higher Density.

So far the available data shows TSMCs 20nm to have higher density, that makes 20nm better than 22nm FF at least in that area. That doesnt translate as 22nm FF being vastly superior. On the contrary, it clearly shows TSMCs 20nm being superior to 22nm FF.

Thats how you extrapolate

 

[AtenRa]

That's irrelevant. AMD have a contract with Globalfoundries, not Samsung.

It also has a contract with TSMC, but yes i dont expect AMD to actually use Samsung's Fabs.

 

[lefty2]

It also has a contract with TSMC, but yes i dont expect AMD to actually use Samsung's Fabs.

Sorry, what I was refering to was the wafer supply agreement

 

[Homeles]

Im the one that has provided numbers to show 20nm being better than 22nmFF and im the one in denial ???

Even if Intels 22nmFF has better electrical characteristics than TSMCs 20nm planar that doesnt make 22nm FF Vastly superior because 20nm has higher Density.

20nm has higher cost/transistor than 28nm. Getting higher density is meaningless if your costs are not going down.

So far the available data shows TSMCs 20nm to have higher density, that makes 20nm better than 22nm FF at least in that area. That doesnt translate as 22nm FF being vastly superior. On the contrary, it clearly shows TSMCs 20nm being superior to 22nm FF.

Thats how you extrapolate

And it's undoubtedly more expensive. Stop focusing on density, and you might actually be able to see the bigger picture.

 

[witeken]

First of all the link you provided doesnt have Intels 22nm FF or TSMC 20nm Planar.

Secondly, i have already provided Metal Pitch numbers for both process that shows TSMC 20nm Metal Pitch(64nm) to be superior against Intels 22nm FF(90nm).

Lets see SRAM Cell size,

Intel 22nm FF = 0.092μm2

TSMC 20nm Planar = 0.081μm2

Almost 12% smaller

Thirdly, nobody have provided any other numbers to support witeken suggestion of Intels 22nm FF being vastly superior to TSMCs 20nm Planar. But according to Metal Pitch and SRAM Cell size, it is TSMCs 20nm process that is superior to Intels 22nm FF making witeken claims incorrect.

If you or others have electrical characteristics of both 20nm and 22nmFF to compare, by all means please post them so we can see which one is the better process.

Until then, TSMCs 20nm is better due to smaller Metal Pitch and SRAM Cell size.

http://seekingalpha.com/article/1848061-intel-vindicated-very-competitive-with-apples-a7

With a little calculation, you can see that Silvermont has a vastly better efficiency than Cyclone.

I can also show you the equal nodes for performance:

Strained silicon:
1st gen - Intel 90 (2004) - TSMC 65 (2007)
2nd gen - Intel 65 (2006) - TSMC 40 (2009)

HKMG:
1st gen - Intel 45 (2007) - TSMC 28 (2012)
2nd gen - Intel 32 (2010) - TSMC 20 (2014)

Tri-Gate:
1st gen - Intel 22 (2012) - TSMC 16 (~EOY 2015)
2nd gen - Intel 14 (2014) - TSMC 10 (~2018)

Post-silicon:
1st gen - Intel 10 (2016) - TSMC 7 (~2021)
2nd gen - Intel 7 (~2019) - TSMC 5 (~2024)

 

[Homeles]

I can also show you the equal nodes for performance:

Strained silicon:
1st gen - Intel 90 (2004) - TSMC 65 (2007)
2nd gen - Intel 65 (2006) - TSMC 40 (2009)

HKMG:
1st gen - Intel 45 (2007) - TSMC 28 (2012)
2nd gen - Intel 32 (2010) - TSMC 20 (2014)

Tri-Gate:
1st gen - Intel 22 (2012) - TSMC 16 (~EOY 2015)
2nd gen - Intel 14 (2014) - TSMC 10 (~2018)

That's a pretty good way to paint how far behind TSMC is, actually.

 

[NTMBK]

Sorry, what I was refering to was the wafer supply agreement

But if they have issues with GloFo meeting demand (like they did with Llano) then they can top up with additional wafers from Samsung. GloFo's supply issues are rumoured to be the reason Llano didn't make it into a Macbook.

 

[AtenRa]

20nm has higher cost/transistor than 28nm. Getting higher density is meaningless if your costs are not going down.

False, cost per transistor is lower than 28nm.

20nm has 1.9x density over 28nm, there is no way 20nm cost is double that of 28nm.

And it's undoubtedly more expensive. Stop focusing on density, and you might actually be able to see the bigger picture.

It is more expensive now compared to 3 year old highly subsided 28nm process.

But cost was not the context of the discussion, and you or anyone else still havent provided anything to counter the numbers i have posted. Which they show 20nm being better than 22nm FF.

 

[teejee]

Also don't forget the fabless + foundry model's cost vs IDM.

There is no cost disadvantage by having product design and production in different companies.
Why do you belive that?

 

[Homeles]

False, cost per transistor is lower than 28nm.

20nm has 1.9x density over 28nm, there is no way 20nm cost is double that of 28nm.

I can't help but take the word of numerous companies over that of an amateur.

It is more expensive now compared to 3 year old highly subsided 28nm process.

But cost was not the context of the discussion, and you or anyone else still havent provided anything to counter the numbers i have posted. Which they show 20nm being better than 22nm FF.

It is a real shame that you cannot grasp how ludicrous your assertions are...

You have decades of industry leadership from Intel, and we get one unclear data point, and you're gleefully claiming that Intel's been beat. What utter insanity. And for what it's worth, Intel's 22nm process has been equally paid off, if not moreso.

I wish there were a nice way to tell someone how wrong they are...

There is no cost disadvantage by having product design and production in different companies.
Why do you belive that?

You keep refuting this, claiming it's basic economics, but the fact is that even the basic tenants of economics are highly debated.

Tri-Gate:
1st gen - Intel 22 (2012) - TSMC 16 (~EOY 2015)
2nd gen - Intel 14 (2014) - TSMC 10 (~2018)

Here's some hard data to back this up:
http://www-inst.eecs.berkeley.edu/~ee290d/fa13/LectureNotes/Lecture15.pdf

Look at slide 18. TSMC has roughly equivalent performance to Intel's 22nm... on a process that won't show up until next year at best. That lines up exactly with your 1st gen FinFET bit -- a 3 and a half year lag. And their PMOS performance is trailing considerably. And it's unlikely that things have moved much since then, since their targets would have already been dialed in, and they'd just be focusing on yields at this point.

 

[AtenRa]

I can't help but take the word of numerous companies over that of an amateur.

None of those companies give cost per transistor. Have a better look.

 

[Homeles]

None of those companies give cost per transistor. Have a better look.

Please give up already. This is getting rather tiring.

 

[jdubs03]

http://seekingalpha.com/article/1848061-intel-vindicated-very-competitive-with-apples-a7

With a little calculation, you can see that Silvermont has a vastly better efficiency than Cyclone.

I can also show you the equal nodes for performance:

Strained silicon:
1st gen - Intel 90 (2004) - TSMC 65 (2007)
2nd gen - Intel 65 (2006) - TSMC 40 (2009)

HKMG:
1st gen - Intel 45 (2007) - TSMC 28 (2012)
2nd gen - Intel 32 (2010) - TSMC 20 (2014)

Tri-Gate:
1st gen - Intel 22 (2012) - TSMC 16 (~EOY 2015)
2nd gen - Intel 14 (2014) - TSMC 10 (~2018)

Post-silicon:
1st gen - Intel 10 (2016) - TSMC 7 (~2021)
2nd gen - Intel 7 (~2019) - TSMC 5 (~2024)

good breakdown. though i'm expecting tsmc-10 in mid-late 2017, probably with their 7nm process in 2020.

 

[Phynaz]

Until then, TSMCs 20nm is better due to smaller Metal Pitch and SRAM Cell size.

Are there any large devices running at 4Ghz built on TSMS's 20nm? :whiste:

 

[Phynaz]

Please give up already. This is getting rather tiring.

He's the founding member of the AMD Defense League. If AMD announced tomorrow that they were going to use GM as their fab suddenly GM would have the best process :biggrin:


Insulting other members is not allowed here
Markfw900

 

[AtenRa]

Please give up already. This is getting rather tiring.

The above figures are not calculated at the same yields for all the processes.

Never mind the FD-SOI on the graphs bellow, concentrate only on bulk.

Add the following,

http://www.techdesignforums.com/blog/2014/06/03/qualcomm-optimises-mask-cost-20nm/

Altered design rules

By changing the design rules and working on computational lithography techniques such as source-mask optimization, Qualcomm and TSMC managed to reduce the minimum pitch for a local interconnect layer that could be patterned by one mask instead of two to 80nm – enough to fit the 20nm process.
At IEDM, Yeap claimed around nine critical mask layers were taken out compared to the initial definition of 20nm and 14nm/16nm finFET processes. Things appear to have changed a little. Layout optimization and process improvements have led to the decision to employ three masks for the combined local interconnect layers, with double patterning used on lower metal layers at a pitch of 64nm. To assist density, the team opted for an 80nm pitch on the next set of routing layers that could be performed using the one mask again. According to Qualcomm: “The resulting technology is more cost effective compared to 28nm HKMG processes and is cost-competitive versus 28nm polySiON.”
To avoid coloring problems with the double-patterned 64nm-pitch M1 layer, Qualcomm adopted an approach in which traces from abutting cells could share the same colour – using relaxed 90nm pitch. For yield-sensitive parts of the design, the pitch could be relaxed to 95nm to allow single-color patterning. According to Qualcomm, the double-patterned parts of the design are to be used primarily for maximising the density of the core IP blocks, allowing random logic and routing to use a more relaxed pitch.
In the routing layers, by relaxing the interconnect pitch from 80nm to 90nm, designs experience 10 per cent less wire delay and need fewer buffer insertions. Qualcomm expects to use this in higher-performance cores within an SoC.
As well as providing a platform based on high-k, metal-gate transistors for 20nm, Qualcomm expects the BEOL developments used for the process to speed up the yield ramp for its move to TSMC’s 16nm finFET process – as the two will share the same interconnect characteristics. Qualcomm reckons that the yield-learning process could be accelerated by up to six months.
The combination of design and lithography tweaks yield two-fold increase in a transistor density over the 28nm process, Qualcomm claims.

Now, you have the wafer cost of both 28nm and 20nm, and you know that 20nm has 1.9x density over 28nm. It is not difficult to see that cost per transistor is lower for the 20nm.

Edit:

Just to make it more clear, lets see 100mm and 200mm die costs.

If at 100mm you have 1000 transistors at 28nm, then at 20nm you have 1000 x 1.9 = 1900.
100mm Die cost at 28nm according to the above table is $5,29
100mm Die cost at 20nm according to the above table is $7,62

Now do the math and see how much each Transistor cost at 28nm and 20nm.

I believe you will find cost per transistor is lower at 20nm

 

[witeken]

good breakdown. though i'm expecting tsmc-10 in mid-late 2017, probably with their 7nm process in 2020.

I expect 10nm towards the second half of 2018. The reason for is that a TSMC confirmed 10nm is planned to launch 2 years after 16nm, like Moore's Law predicts. However, today Moore's Law isn't really 2 years anymore, so you should add an arbitrary number of months.

 

[Homeles]

I'm still not seeing how your singular data point trumps a handful of others, like from Nvidia, ARM, and the graph I linked above.

He's the founding member of the AMD Defense League. If AMD announced tomorrow that they were going to use GM as their fab suddenly GM would have the best process :biggrin:

I just don't understand why people here are permitted to pose as experts, even though they clearly are not. It's great that there are people here that are passionate about certain companies, but it's taken so often to the extreme here. Take the guy from the VIA thread for example... or the couple guys that are hyping the crap out of Tegra K1...

...and then there' s the AMD Defense League, as you mentioned. Credit should be given where it's due, and AMD certainly has made their victories over the years, but they don't win every single match up -- and that's okay, nobody wins all of their battles -- but it's not for them.