It's an old myth that the best chips are in the center of the wafer. ALL chips are tested and speed binned. A 2600k could come from any spot on the wafer.
* Not speaking for Intel Corp *
It's not really a myth, but the applicability for the statement is periodic in time. That periodicity coincides with the timing of the transition from one wafer size to the next leading edge wafer size.
And the reasoning for this periodicity was, historically, that leading-edge development tools almost always were extensions of the then existing toolset platform.
For example when we transitioned from 6" to 8" wafers in R&D the majority of our 8" R&D toolsets were essentially 6" toolsets with the robotics scaled up (handling) and chambers scaled out but the sources (be it the implant targets, the litho optics, the spin-coat dispensers, the etch chamber RF source, the ash chamber source) and the starting point for your recipe set was usually whatever was optimized for yields at 6".
This repeated itself at the 8" to 12" transition. It was even replicated in some of the production tools. For example Mattson's 300mm asher was actually a 200mm asher RF system bolted into a 300mm handling and vacuum chamber (I'm grossly oversimplifying here) but the net effect was a very asymmetric plasma density profile at the wafer surface owing to the 200mm pedigree in the RF source plumbing.
And as was the case in the 4"->5", and 5"->6", and 6"->8", and 8"->12" transitions, the more nodes you got "into" each wafer size the more likely the toolsets were to be developed for that specific wafer size and the center-to-edge
toolset-induced bias dissipated for solid engineering reasons.
300mm is a very matured market now, the toolsets have well since left behind their 200mm baggage and nowadays the types of center-to-edge effects that are dominate are generally related to wafer bowing (from stress engineering) and edge effects the come into play in plasma densities as well as defectivity (edge peeling or delamination of deposited films, etc).
It's there still, just highly minimized compared to what it use to be like.
And rest assured that when we transition to 450mm the center-vs-edge reality will rear its head again. It's endemic to the nature of process development and toolset development for the industry. But it won't be as severe as past wafer transitions. Just as the ramp to entitlement yields occur faster with every node because people get better at the business so to do they get better every transition at managing the discontinuities in those transitions.