Man, with the delay in EUV, 14nm and below are sucking pretty hard. Wouldn't want to be a process engineer at Intel right now - the OT must suck as well.
640 and 650 you mean.
Man what a shame: 6 core + eDRAM could have been a nice option against Zen/Zen+ on mainstream desktop.
So do you lose the benefit of e-dram as a cache if you add a dgpu?
Interesting challenges to solve, what's not to like?
Should we blame Kraznich or AMD? Maybe Zen will light a fire under his arse and we get more than the 5% annual performance increase that Anandtech loves to call " The New Out-of-the-box Performance Champion".
BK said they are cutting back on PC R&D. Zen's not going to change that.
BK said they are cutting back on PC R&D. Zen's not going to change that.
Can't see that myself - medium term its a commodified market, so near dead by Intel's standards. Any R&D response now obviously wouldn't appear in products for quite a while, by which time it may well not matter.
They're obviously not going to stop or slow down in terms of server chips though.
But the cores are diverging (avx512), i assume the laptop and desktop parts will keep the ringbus and the big server SOC's move to the new fabric etc.Server chips use the same cores/IP that are used in PCs. Cutting back on CPU core development would hurt server, but Intel says it's increasing investments in servers.
Intel isn't cutting back its CPU core investments.
But the cores are diverging (avx512), i assume the laptop and desktop parts will keep the ringbus and the big server SOC's move to the new fabric etc.
if they make the server core a true 512bit wide core then they massively diverge, almost everything has to change and if they implement non mirco coded scatter gather then cache and load store will have to be very very different.The cores are diverging somewhat but even SKL Xeon is based on the fundamental Skylake core with some modifications/addition.
If you cut back R&D on the fundamental cores, you don't have as strong a foundation to work with for server. This is an area that Intel has been frantically investing in (servers) so they will want to do everything in their power to keep cores hyper competitive.
If you put Intel's main CPU architectures next to its last two CEO's you get a rather worrisome picture.
Otellini CEO from 18-05-2005 to 04-06-2013
in this timeframe we saw:
the move away from Pentium and Netburst with Core branding and Yonah (jan 2006)
then the ground up Core design with Conroe (jul 2006)
then we got SMT with Nehalem (nov 2008)
Sandy Bridge (jan 2011)
Haswell (debuted 04-06-2013...)
For anyone saying Conroe was in developement for much longer than his tenure as CEO, yes indeed and Otellini was one of the driving forces behind it. That's also why I included Haswell with Otellini, it was has final, goodbye tock.
Krzanich CEO from 04-06-2013 to present:
....still waiting for something substantial.
Jim Keller already made some hints about the IPC potential of the ARM architecture.
Given that ARM is a RISC architecture, does it not need higher IPC or clockspeed in order to match CISC performance?
Apple's A10 already has higher ST performance per clock versus Skylake according to Geekbench. I'm expecting the K12 to match that
The Ghost Arch that was not heard from for a year already?AMD's K12
You are talking like if they didn't take in count power consumption at "lower clocks" in a mobile SOC when Intel couldn't get even close to this efficiency curves with an advantage in manufacturing process.It's always easier to get high IPC at lower clocks. Call me again when they achieve this at 4 ghz (or 5 gz OCed like Kaby lake).
The Ghost Arch that was not heard from for a year already?
You are talking like if they didn't take in count power consumption at "lower clocks" in a mobile SOC when Intel couldn't get even close to this efficiency curves with an advantage in manufacturing process.