[Semiwiki] Intel 450 mm wafers delayed until 2023, other SPIE News

[Fjodor2001]

https://www.semiwiki.com/forum/content/3241-intel-450mm-delayed-until-2023.html

Intel 450 mm wafers delayed until 2023:

The first interesting information from the conference floor was that 450mm is being pushed out. What I heard is that with low fab utilization and the empty fab 42 shell, Intel has pulled all of their resources off of 450mm. Intel was one of the key players pushing 450mm and the comments I heard were 450mm won’t be this decade with 2023 as the new introduction date for high volume manufacturing. Some equipment companies appear to be putting 450mm equipment development on hold.

The article also contains lots of other interesting semiconductor related info, such as:

Interestingly there seemed to be a lot of optimism that we can achieve the 10nm, 7nm and possibly 5nm nodes by combining multi patterning with other techniques. There were a lot of papers on novel multi patterning schemes and shrink technologies. New immersion systems discussed by ASML and Nikon are promising 250 wafers per hour reducing exposure costs. There is a lot of work being done on simplification of the schemes. There is also help from the design and process technology side with increasing use of gridded designs and 3D memory. In 2013 Samsung introduced a 3D NAND technology that achieved bits/cm2 density similar to 1x NAND using a roughly 50nm lithography technology. The ability to scale memory in third dimension is a kind of equivalent scaling technique that can continue “scaling” with less pressure on exposure systems.

In the future please label the sources of rumors when posting them here
-ViRGE

 

[witeken]

That's just a rumor, and really not a credible. Brian Krzanich said in the October earnings call that 450mm is planned for ~2018: Intel Will Not Reconsider Timing for 450mm Manufacturing.

 

[Homeles]

We've already discussed this rumor in this thread: http://forums.anandtech.com/showthread.php?t=2368771

 

[Fjodor2001]

We've already discussed this rumor in this thread: http://forums.anandtech.com/showthread.php?t=2368771

That thread has the topic "Intel 14nm Delayed (Again)", so it's somewhat off-topic there. Also, I think the 450 mm wafer delay (and the rest of the info in the OP article) is important enough to mandate it's own thread.

 

[jpiniero]

Chip Stacking on older nodes is the way to go. That is, if they can make it work. I imagine integrating the rest of a system (ie: networking/NV Memory/etc) would be easier if you could just stack, and a $30 chip that wouldn't need much else to build a system would be appealing to OEMs.

 

[DigDog]

the future is a RAIC .. lol. not 10nm.

multi-socket at consumer level, and onboard controllers to divide the workload.

300 cores by 2020. FTW
(^speculation of the highest order)

 

[Homeles]

the future is a RAIC .. lol. not 10nm.

Those things are wholly separate. Seriously, the garbage people write...

 

[jhu]

300 cores by 2020. FTW
(^speculation of the highest order)

We already have them. They're called "GPUs". Unfortunately their branch predictors suck.

 

[Homeles]

Do GPUs even have branch prediction?

 

[jhu]

Do GPUs even have branch prediction?

They don't. They just execute and pick the the correct answer later, or something like that.

 

[Fjodor2001]

Chip Stacking on older nodes is the way to go. That is, if they can make it work. I imagine integrating the rest of a system (ie: networking/NV Memory/etc) would be easier if you could just stack, and a $30 chip that wouldn't need much else to build a system would be appealing to OEMs.

But won't chip stacking increase cost, compared to shrinking nodes? I imagine that there will have to be more process steps to build layer upon layer.

Also, what if one layer fails in production, then I assume you'll have to fail the complete chip, so you can get yield issues?

 

[KingstonU]

Also, what if one layer fails in production, then I assume you'll have to fail the complete chip, so you can get yield issues?

That is a very good point! Will we have even further product stacking based on the number of functional layers as well as functional cores?

AMD-Athlon-X12 with 3 layers x 4 cores per layer. But not all the cores on every layer works according to spec.

Think of the crazy number of working variations that will come out of the oven!

 

[Unoid]

That is a very good point! Will we have even further product stacking based on the number of functional layers as well as functional cores?

AMD-Athlon-X12 with 3 layers x 4 cores per layer. But not all the cores on every layer works according to spec.

Think of the crazy number of working variations that will come out of the oven!

we won't find dense sub 20nm cpu's or other like logic stacked. Where do you think the heat will go?

 

[jpiniero]

we won't find dense sub 20nm cpu's or other like logic stacked. Where do you think the heat will go?

Clearly you would have to cut clock speeds and ST performance would be hurt. Something like Steamroller or even Core wouldn't really be suitable for it. But the cost savings in theory would make it worthwhile.

 

[NTMBK]

lol Semiwiki.

 

[Fjodor2001]

lol Semiwiki.

As in SemiconductorWiki, not to be confused by e.g. SemiAccurate or similar. Just sayin'.

 

[Homeles]

As in SemiconductorWiki, not to be confused by e.g. SemiAccurate or similar. Just sayin'.

As a news site, it's just as bad, if not worse. Charlie's a douchecanoe, but he's usually right.

 

[Fjodor2001]

As a news site, it's just as bad, if not worse. Charlie's a douchecanoe, but he's usually right.

I think you should check out SemiWiki here, it actually contains quite a lot of interesting articles.

A lot of the bloggers there are professionals from the semiconductor industry. See the About here.

 

[Homeles]

As a news site

:thumbsup:

 

[erunion]

As in SemiconductorWiki, not to be confused by e.g. SemiAccurate or similar. Just sayin'.

Semiwiki has earned itself a bad reputation all on its own. (For parading baseless rumors as news)

 

[mrmt]

As in SemiconductorWiki, not to be confused by e.g. SemiAccurate or similar. Just sayin'.

Semiwiki is TSMC paid PR

 

[Fjodor2001]

Well it seems credible enough to have been picked up by numerous other sites, for example:

http://www.electronicsweekly.com/ne...yed-till-2023-450mm-euv-light-source-2014-03/

http://www.computerbase.de/news/2014-03/450-mm-wafer-erst-2023-euv-ebenfalls-verspaetet/

http://www.sweclockers.com/nyhet/18...afers-pa-450-millimeter-senarelaggs-till-2023

 

[Homeles]

Well it seems credible enough to have been picked up by numerous other sites, for example:

http://www.electronicsweekly.com/ne...yed-till-2023-450mm-euv-light-source-2014-03/

http://www.computerbase.de/news/2014-03/450-mm-wafer-erst-2023-euv-ebenfalls-verspaetet/

http://www.sweclockers.com/nyhet/18...afers-pa-450-millimeter-senarelaggs-till-2023

Those sites post whatever garbage they can get their grubby little hands on. Welcome to the sad state of the internet.

 

[Fjodor2001]

Those sites post whatever garbage they can get their grubby little hands on. Welcome to the sad state of the internet.

Not true, those sites are usually correct in what they publish.

 

[mrmt]

Well it seems credible enough to have been picked up by numerous other sites, for example:

http://www.electronicsweekly.com/ne...yed-till-2023-450mm-euv-light-source-2014-03/

http://www.computerbase.de/news/2014-03/450-mm-wafer-erst-2023-euv-ebenfalls-verspaetet/

http://www.sweclockers.com/nyhet/18...afers-pa-450-millimeter-senarelaggs-till-2023

And these sites are not worth a dime. This is what Eletronics Weekly is writing about EUV:

And the only known way to shrink cost-effectively after 28nm is EUV, and that may not happen ever…

And this is what ASML was saying in the last Q&A with their investors:

http://seekingalpha.com/article/1960051-asml-holding-nv-management-discusses-q4-2013-results-earnings-call-transcript?source=nasdaq

During the quarter, we recognized revenue for our first NXE:3300 EUV system. Overall, last quarter of unit shipment were more balanced between ArF immersion and KrF than the prior quarter, indicating the addition of wafer capacity. As a result, the ASP of EUR 25.7 million for all systems sold in Q4 was lower than Q3 at EUR 28.2 million.

(...)

In 2014, we expect to deliver the remaining 8 EUV systems on order. In Q1, we expect to ship 1 EUV system. As with all new technology introductions, revenue recognition of EUV system is currently taking place after installation and customer acceptance. This revenue recognition method will continue until we demonstrate predicable installation timing.

(...)

We are very satisfied with the acceptance of our NXT:1970 as the most advanced lithography solution in the industry and as a viable choice for the 10- nanometer logic node. However, we realized, together with our customers, that the continuation of further shrink, therefore, Moore's Law, ultimately and inevitably depends on the introduction of EUV. We are therefore working very closely with selected customers on the industrialization of our EUV technology, which we will very likely adopt when their economic targets for initial insertion of these more cost-effective solutions are actually met, thereby optimally addressing the economic and cost challenges of this node.

So there you got it. EUV is slow, but is going forward, and ASML expectations are to field it with the 7nm node, which is is.... 2018 according to Intel's plan, in line with what the CEO has been saying. And once EUV is online 450nm becomes feasible.

So there you got it, you have TSMC paid PR spreading FUD on the market and a bunch of half a dime sites backing it up on one side, and ASML and Intel management boards telling another story to their investors on the other. Do I need to add anything else?