Bulldozer "cores" are not true cores
Y our comments are pissing me off the point where I actually registered here.
the adjoining of parts of the "core" was to save die space, it is still a dual core. the FPU can either be s 128 bit fpu's (comparable to intel) or one massive 256b fpu. It was a great way to save die space. the pipeline is a bit longer then stars, but it is also WIDER.
the whole design is actually very optimized. It should be a capable performer.
First of all it is NOT a dual core, as each "core" is really a hardware thread similar to HyperThreading (in CMT each has a dedicated hardware tread called "cluster"). Did you check my previous post? Those comments comes from Andy "Krazy" Glew (the designer of CMT) and Chew* (an overclocker who has handled Bulldozer CPUs, and overclocked an AMD FX to 8.43GHz). If you want to read more about CMT origins, then I suggest you look at Andy Glew's article on Bulldozer.the adjoining of parts of the "core" was to save die space, it is still a dual core. the FPU can either be s 128 bit fpu's (comparable to intel) or one massive 256b fpu. It was a great way to save die space. the pipeline is a bit longer then stars, but it is also WIDER.
the whole design is actually very optimized. It should be a capable performer.
Classy, with all due respect the problem we may face with a fairly low IPC (assumed given the pricing structure) is that we won't have any cut and dry winners per se.
Reason :
Mediocre IPC + lots of pseudo-cores (I don't consider a 2600k an 8-core either, not even close) = great at apps that can use all 8 cores, not so great in others, should be good at heavy multitasking so long as the cache and memory performance is adequate.
vs.
Maximum IPC + quad core (forget HT) = excellent at almost everything, and can even get a boost on heavy multithreading because processes will finish more quickly if performance per core is higher.
So what we're left with is this :
Games may run XX% faster on See where this is going?
Y our comments are pissing me off the point where I actually registered here.
Then why physically the Llano Core and the "Bulldozer" Cores about the same size?
(Integer Cluster ^)
You have 8 Llano cores(in size only) in the Bulldozer Physically
The Front end went from xmm wide to x(2)mm wide
Let me quote Chew* from here....Then why physically the Llano Core and the "Bulldozer" Cores about the same size?
(Integer Cluster ^)
You have 8 Llano cores(in size only) in the Bulldozer Physically
The Front end went from xmm wide to x(2)mm wide
Having a Floating Point doesn't make it a "core" the Floating Point has always been an additive component
Integer Core + Floating Point doesn't make it a core
Integer Core makes it a core
This is exactly what I find when trying to show the truth. More quotes from Chew* here.....Like i said before I discussed this face to face with engineers at AMD, BD is a native 4 core 8 thread part.
and then the lynch mob got mad..........
Why is there still an on going discussion of core's modules.........
I don't give a rats ass what Marketing calls the chip.
AMD's patent draws a clear picture. They say a picture says a 1000 words right? AMD's own picture for there own patent.
Note core 100 not module 100 aka core 0, and then inside core 0 is 2 clusters A and B.
Case closed.
quoted
First of all it is NOT a dual core, as each "core" is really a hardware thread similar to HyperThreading (in CMT each has a dedicated hardware tread called "cluster"). Did you check my previous post? Those comments comes from Andy "Krazy" Glew (the designer of CMT) and Chew* (an overclocker who has handled Bulldozer CPUs, and overclocked an AMD FX to 8.43GHz). If you want to read more about CMT origins, then I suggest you look at Andy Glew's article on Bulldozer.
Then why physically the Llano Core and the "Bulldozer" Cores about the same size?
(Integer Cluster ^)
You have 8 Llano cores(in size only) in the Bulldozer Physically
The Front end went from xmm wide to x(2)mm wide
Having a Floating Point doesn't make it a "core" the Floating Point has always been an additive component
Integer Core + Floating Point doesn't make it a core
Integer Core makes it a core
I understand that. My point was that the FPU either split or combined, should at least on paper, be better then current Intel offerings. However without benchmarks to back it up. Its just speculation.
The FUD needs to stop. thats not directed at you either.
That's marketing talk. Both Andy Glew and Chew already said that ("cores" was a marketing strategy). Chew had talked to engineers, and Andy Glew is an engineer himself.And AMD "Software" Engineers say it's 8 cores
First of all it is NOT a dual core, as each "core" is really a hardware thread similar to HyperThreading (in CMT each has a dedicated hardware tread called "cluster"). Did you check my previous post? Those comments comes from Andy "Krazy" Glew (the designer of CMT) and Chew* (an overclocker who has handled Bulldozer CPUs, and overclocked an AMD FX to 8.43GHz). If you want to read more about CMT origins, then I suggest you look at Andy Glew's article on Bulldozer.
First of all it is NOT a dual core, as each "core" is really a hardware thread similar to HyperThreading (in CMT each has a dedicated hardware tread called "cluster"). Did you check my previous post? Those comments comes from Andy "Krazy" Glew (the designer of CMT) and Chew* (an overclocker who has handled Bulldozer CPUs, and overclocked an AMD FX to 8.43GHz). If you want to read more about CMT origins, then I suggest you look at Andy Glew's article on Bulldozer.
That's marketing talk. Both Andy Glew and Chew already said that ("cores" was a marketing strategy). Chew had talked to engineers, and Andy Glew is an engineer himself.
That's marketing talk. Both Andy Glew and Chew already said that ("cores" was a marketing strategy). Chew had talked to engineers, and Andy Glew is an engineer himself.
1.4.1 Multi-Core Processors
AMD Family 15h processors have multiple compute units, each containing its own L2 cache and two
cores. The cores share their compute unit’s L2 cache. Each core incorporates the complete x86
instruction set logic and L1 data cache. Compute units share the processor’s L3 cache and
Northbridge
Software Engineers lying to people highly doubt itAMD Family 15h processors include many features designed to improve software performance. The
internal design, or microarchitecture, of these processors provides the following key features:
• Up to 8 Compute Units (CUs) with 2 cores per CU
Yet its not. Just becuase someone says something, doesn't make it true. also Andy Glew resigned/was let go from AMD. Likely for reasons we don't understand. So stop dredging in hearsay and produce evidence by way of core diagrams logic construction etc or STFU.
Whether you believe them or not is up to you, but this is the real stuff. And its not only Andy Glew who said that, also another ex-AMD engineer Cliff Maier said almost the same thing. And just like Chew* said "the lynch mob got mad".That is a funny link you have:
"The only bad thing is that some guys I know at AMD say that Bulldozer is not really all that great a product, but is shipping just because AMD
needs a model refresh. "Sometimes you just gotta ship what you got." If
this is so, and if I deserve any credit for CMT, then I also deserve
some of the blame. Although it might have been different, better, if I
had stayed. "
Its the worst story ever written. My children wouldnt even beliewe it. Highly unprofessional.
Have you gone thru the most of the stuff in that link? It also highlights possible weaknesses in the CMT design. :hmm:Whose to say that they followed his design 100% ??? I doubt they did. secondly we know they didn't because looking at his proposal and the difference in the core diagram, reveals that AMD thought part of his idea had merit, and obviously alot of it didn't.
your trying to infer numerous things that simply are not true. things like bulldozer is a low IPC design, I don't see that. to me bulldozer appears to be a balanced design. It really reeks of GPU cluster design, which leads me back to my previous assessment, CMT is not the underlying principal and its only part of the design.
Hardware engineers and software engineers have a different take on the "cores". That's because to software engineers each thread behaves like a "core".Software Engineers lying to people highly doubt it
Marketing didn't come up with the module/cores idea it came from the Engineers who developed the processor
Hardware engineers and software engineers have a different take on the "cores". That's because to software engineers each thread behaves like a "core".
Have you gone thru the most of the stuff in that link? It also highlights possible weaknesses in the CMT design. :hmm:
Hardware engineers and software engineers have a different take on the "cores". That's because to software engineers each thread behaves like a "core".
Whether you believe them or not is up to you, but this is the real stuff. And its not only Andy Glew who said that, also another ex-AMD engineer Cliff Maier said almost the same thing. And just like Chew* said "the lynch mob got mad".
I'm actually getting tired of this discussion...
Single thread doesn't matter!!!!
2-4 threads matter!!!
Will a high performing chip with 4cores perform high in 2-4threads? yes.
What if we take the example of BD?
1 thread BD(4,2GHz) 15% slower then SB (3,8Ghz)
2 threads BD (4,2Ghz) 12% slower then SB(3,7GHz)
3 threads BD (4,2Ghz) 9% slower then SB(3,6GHz)
4 threads BD (4,2Ghz) 5% slower then SB(3,5GHz)
(so what has ipc to do with performance? giving a certain cpu can be 20% higher clocked in some scenario's... ipc has become a metric, but lost a big chunck of its importance when the cpu's were clocked similarly. This is actually a reinvention of the discussion betzeen Athlon Tb and p4 and later..).
So how will single thread performance determine the actual performance in real life scenarios? it doesn't anymore. Because of turboboost every cpu is all over the place. The on who can remain in turbo the longest for the most threads will either bring the gap extremely close or will have an edge.
In the above example ipc is 15% slower than SB, yet when looking to the 2-4thread scenario we talk about ~9% real life difference. Thats alot less than any single thread would indicate.
So please stop with the rubbisch about single thread performance to determine multithread performance but start looking at multithreads to do that. Single thread as a metric has become obsolete in years, almost everything has 2 or more threads, so start using those apps as a metric.
Rest assured, if SB is faster at 3,8Ghz bymore than 10% you won't see AMD winning in those thread scenarios, so you don't have to dismiss them!!! you can still yell about how superior SB is!!! But than at least the stupid single thread importance is of the table.
Well here I am, the lynch mob, as you label us.
In a house with 6 Intel computers, 2 of wich is SB, no AMD.
And then you bring your old bitter men. The "real stuff". Ex employees, the last one you quoted say bobcat was a bad business. Ok so 74mm2 beating an larger Atom 60% in single threaded performance !
He say he didnt know the bobcat team. They were young. They had no experience in sub 10w. ROLF. Now we know the 60% results. Its good he is not at AMD anymore. And i can say i can live without his experience, because my Atom is just a pain for a PC.
Your ramblings make no damned sense at all. Just due to the nature of many applications not being multithreaded, and many more focusing heavily on one main core (eg; most mp-optimized games), single-thread performance will have an important role for a long time to come.
Btw, I am not saying that SB is superior to BD, as we have no confirmed benches. I expect BD to be noticably worse in gaming and a few things, and to really show its abilities by defeating SB in things like encoding and very aggressively multithreaded apps.
I swear we've had an influx of AMD paid marketers of late. I have an AMD GPU, and have bought tons of AMD CPUs over the years, I want to have BD be a good choice as well, but this ludicrous hype and fanboy combat mentality has to stop. And statements like 'single-thread doesn't matter', and 'ipc doesn't matter' are insanely stupid. It sounds like the people defending the P4 Willamette vs. the Athlon Thunderbird and XP, when the AMD was faster in almost every real-world scenario, yet the P4 had a higher clock speed. Woopdy doo.
BD is not a p4, IPC is important, core count is important, fpu performance is important. I'd say the converse is true about the marketing people though.
More FUD being thrown at BD then coming to its rescue. Most of the "AMD Fanbois" as you claim them. Have all been saying the same thing.
Show us the benchmarks.
I will reserve my judgment until benchmarks arrive. Same thing everyone else should be doing. But calling BD a P4 is completely ignorant.
In module BD run threads in parallel, SB in HT don't. Is this correct?