September 22nd ETA for AMD FX processors

[NostaSeronx]

There, I fixed it for you. The FP unit is really 2x128-bit FMACs, not true 256-bit (both 128-bit FMACs combined for 256-bit operations when required).

It's true 256bit

You are in denial, despite the mounting evidence I've shown coming directly from the creator of CMT and an overclocker who had handled Bulldozer and spoke to AMD's engineers.

The general consensus from AMD is that it is two cores

The general consensus from Engineers is that it is two cores

Even Engineers outside of AMD call it two cores

Why are you bringing GPUs into the equation? NVIDIA GPUs have drivers (custom/specifically written for the hardware) and also SDKs like CUDA to support GPGPU functions (used in specialized software like F@H, and especially those dealing with HPC). That is a whole different subject.

It's called SMP look it up it's the future or the present I should say we aren't in 1999

 

[Dresdenboy]

I was referring to the core, not the processor overall as every design is different (e.g.: Conroe uses FSB interface, K8 uses HyperTransport and IMC, Nehalem use QPI and IMC, etc).

Yes, it can execute (decoded) raw ops. But without the fetch mechanism, nothing is feeding the schedulers. :hmm:

But does a "core" have to? What is the definition of what a "true core" has to be capable of?

Sun's Niagara uses CMT (mostly clusters of ALUs) rather than SMT.

You are right, it's not SMT, it's Fine Grain Multithreading (barrel processor) in T1. Only later generations (T2 or T2 Plus?) brought SMT.
http://en.wikipedia.org/wiki/File:Pipeline_Niagara.svg
So there is support of 4 threads per core in Niagara. What you mean by CMT is their sharing model of units for multiple such cores. Overall they state Chip Level Multithreading (which is not AMD's Cluster-based MT or Glew's MCMT) as being a combination of multiple cores supporting (S/FG)MT:
http://www.cs.wm.edu/~kemper/cs654/slides/niagara.pdf

Currently most software (outside of specialized and custom ones) do not support FMA4, re-compilation and compiler support are required. Just like 3dNow! (which is an extra AMD feature) which is hardly or almost never used (most software went in favor of SSE and SSE2).

Today is a different situation than back in the 3DNow! days: there are more and better (compared to other products at the same time) compilers supporting FMA available plus the HPC crowd is going to use it.

 

[BlueBlazer]

It's true 256bit

It is not (as mentioned earlier).

The general consensus from AMD is that it is two cores

The general consensus from Engineers is that it is two cores

Even Engineers outside of AMD call it two cores

That's AMD's marketing of "cores". General consensus? You are dreaming. Any experienced chip designer/engineer already well versed with CPU architectures, already knows what they are looking at (and these are not cores).

It's called SMP look it up it's the future or the present I should say we aren't in 1999

Huh? Now you bring in "Symetric Multi-Processing"? What does it have to do with NVIDIA GPUs (and FMA)? :hmm:

Today is a different situation than back in the 3DNow! days: there are more and better (compared to other products at the same time) compilers supporting FMA available plus the HPC crowd is going to use it.

As mentioned earlier "specialized and custom ones" (with HPC being in this category). Other than that, desktop applications and games are not likely to see FMA (and XOP) in action.

 

[NostaSeronx]

It is not.

It is both cores can execute 256bit Floating Point and 256bit Integer

It's actually a 512bit Maths Coprocessor with a 256bit fp portion and a 256bit int portion

That's AMD's marketing of "cores". General consensus? You are dreaming. Any experienced chip designer/engineer already well versed with CPU architectures, already knows what they are looking at (and these are not cores).

A well versified CPU architect would know his roots

That a Fetch and a Decode portion of a Processor isn't part of a Core :whiste:

Processor = Fetch/Decode/Core/Math Coprocessor today but the cores definition hasn't changed

AMD "Bulldozer" Processor which is a single Compute Unit that has a interesting Fetch Unit and Decode Unit that can feed Two Cores Simultaneously and which those Two cores feed the same Math Coprocessor

Wow...doesn't take much brains to figure its a dual core and a modern CPU processor

The original computer processors the fetch was done by hand and the decode done by a calculator which would convert what you wrote into computer language you would then take that paper and feed into a other calculator this what is called a core you will either find your answer or you would have to feed it into another calculator

Huh? Now you bring in "Symetric Multi-Processing"? What does it have to do with NVIDIA GPUs (and FMA)? :hmm:

Folding @ Home will use FMA4 just like it does for GPUs
SMP in F@H has support for FMA4, already...

As mentioned earlier "specialized and custom ones" (with HPC being in this category). Other than that, desktop applications and games are not likely to see FMA (and XOP) in action.

Multimedia and A future physics engine will :whiste:

Having a 256 FMA is like an Add and a Multiply that happens at the same time with all the performance you expect

 

[BlueBlazer]

It is both cores can execute 256bit Floating Point and 256bit Integer

It's actually a 512bit Floating Point

Huh? 512-bit? You need to take those rose colored glasses off... :hmm:

A well versified CPU architect would know his roots

That a Fetch and a Decode portion of a Processor isn't part of a Core :whiste:

And if you don't have them, then the "core" cease to function. Every section is dependant on each other to function as a whole.

The first Fetch Units and Decode Units weren't part of the first microprocessors they were a separate unit like the floating point unit

Huh? They are not separate. For example early ancient CPUs contains Instruction Decode ROM, which is a pre-cursor to the decode unit.

Folding @ Home will use FMA4 just like it does for GPUs
SMP in F@H has support for FMA4, already...

Multimedia and A future physics engine will :whiste:

Having a 256 FMA is like an Add and Multiply to happen at the same time with all the performance you expect

Do you know what generally SMP is? Even operating systems like Linux and FreeBSD implemented it. I think you are clueless as usual.

 

[NostaSeronx]

Huh? 512-bit? You need to take those rose colored glasses off... :hmm:

Move Elimination is a 4 way 128bit SSE "Move" aka a 512bit "Move"

Maybe you need to get off your intel chair

And if you don't have them, then the "core" cease to function. Every section is dependant on each other to function as a whole.

The core ceases to function but it is still a core don't be a dumbass you just said core you proved by accident what I just said

Huh? They are not separate. For example early ancient CPUs contains Instruction Decode ROM, which is a pre-cursor to the decode unit.

Military Computers are the first computers that had a fetch which was done by hand a decode done by a special computer that had a caculator and a really big computer that figured out the answer

Do you know what generally SMP is? Even operating systems like Linux and FreeBSD implemented it. I think you are clueless as usual.

You are the clueless one :whiste:

 

[MisterMac]

@NostaSeronx

Why don't you seriously just provide Proof?!



EVERY single article on BD states the following:

Each bulldozer module with 2 Integer Cores and 2x128BIT FMA FPU.

How [redacted] does that equal 512 bit FPU instructions?

Stop being retarded.


Show some AMD spec saying this specificly, simple.
OR shut up.

EDIT:
by Move Elimination Logic 8x 64bit = 512 BIT.

Just doesn't translate into single cycle operations with 512bit, just doesn't.
By the recogning we have 1028 bit already.

No profanity please. And while we're at it, drop the hostile attitude.

-Thanks
ViRGE

 

[NostaSeronx]

@NostaSeronx

Why don't you seriously just provide Proof?!



EVERY single article on BD states the following:

Each bulldozer module with 2 Integer Cores and 2x128BIT FMA FPU.

How the fuck does that equal 512 bit FPU instructions?

Stop being retarded.


Show some AMD spec saying this specificly, simple.
OR shut up.

I can't somebody is wrong on the internet

Also there are 4 pipes

4 pipes for 4 128bit units

 

[BlueBlazer]

AMD "Bulldozer" Processor which is a single Compute Unit that has a interesting Fetch Unit and Decode Unit that can feed Two Cores Simultaneously and which those Two cores feed the same Math Coprocessor

Wow...doesn't take much brains to figure its a dual core and a modern CPU processor

I'm beginning to see now, you are stuck with "cores". That's all you can see and understand (despite the information presented). It doesn't take much brains to figure out how delusional you are. :hmm:

The original computer processors the fetch was done by hand and the decode done by a calculator which would convert what you wrote into computer language you would then take that paper and feed into a other calculator this what is called a core you will either find your answer or you would have to feed it into another calculator

LOLOLOL! Gonna use this as siggy....

Speaking of delusion, you must be delusional to think it's okay to call people names in the CPU forum. Take it down a notch.

-Thanks
ViRGE

 

[NostaSeronx]

I'm beginning to see now, you are stuck with "cores". That's all you can see and understand (despite the information presented). It doesn't take much brains to figure out how delusional you are. :hmm:

You are the one stuck on cores

Blasting out because Chew* and some guy who obviously is butt hurt that he lost his job

That they are saying they aren't cores

BIG NEWS! They are wrong, cores are cores Bulldozer is an 8 core processor

Everytime someone says 8 cores you come in

OH LOOK CHEW said this and BUTTHURT MCGEE said this

and are you Terrance by chance anyway?

 

[ViRGE]

Take the snark down a notch. That's how flamewars get started.

 

[MisterMac]

I can't somebody is wrong on the internet

Also there are 4 pipes

4 pipes for 4 128bit units

Cannot translate to raw peformance cycle for 1 512bit instruction.
But do go on.

Your excuse if BD fails to match both fpu performance to a 4 Core SB?

Not so smart.

 

[BlueBlazer]

You are the one stuck on cores

Blasting out because Chew* and some guy who obviously is butt hurt that he lost his job

That they are saying they aren't cores

BIG NEWS! They are wrong, cores are cores Bulldozer is an 8 core processor

Everytime someone says 8 cores you come in

OH LOOK CHEW said this and BUTTHURT MCGEE said this

are you Terrance by chance anyway?

Chew* butthurt that he lost his "job"? Wowzers! Do you know who Chew* is? You are incredibly clueless!

 

[NostaSeronx]

Cannot translate to raw peformance cycle for 1 512bit instruction.
But do go on.

Your excuse if BD fails to match both fpu performance to a 4 Core SB?

You have to understand the 512 bit execution* is a special move execution called "Move Elimination"

I like how you said "if" thanks my excuse for lack of FPU performance would be it's biased and not properly compiled/programmed to effectively use performance enhancing features

http://developer.amd.com/tools/lwp/pages/default.aspx
http://www.anandtech.com/show/2302

Should help a lot in programming for parallelism :whiste:

A 256bit Floating Point Execution can occur per cycle, the delay for an average floating point to get scheduled and execute is 12+ cycles so plenty of time for the other cores 256bit Floating Point Execution to occur

Also 256bit Integer executions can occur per cycle as well but the delay for an average integer command to get executed is 5+ cycles
(This is big news for x264 encoders)

I call the executions but the real term is operation

Chew* butthurt that he lost his "job"? Wowzers! Do you know who Chew* is? You are incredibly clueless!

No the guy you considered to have developed AMD's CMT

 

[BlueBlazer]

No the guy you considered to have developed AMD's CMT

Then why did you include Chew* into the equation? Because he said the same thing? :hmm:

 

[NostaSeronx]

Then why did you include Chew* into the equation? Because he said the same thing? :hmm:

Yes, because you used him as a quote and he provided "unnamed AMD engineer" said to him that AMD Bulldozer is a 4C/8T

When if you look at the die there are 8 cores....so either that AMD engineer doesn't know what a core is or he wasn't an engineer

My conspiracy theory is that it was he who shall not be named, he tricked Donanimhaber and he tricked Chew* and who else will be tricked :sneaky:

 

[BlueBlazer]

Yes, because you used him as a quote and he provided "unnamed AMD engineer" said to him that AMD Bulldozer is a 4C/8T

When if you look at the die there are 8 cores....so either that AMD engineer doesn't know what a core is or he wasn't an engineer

My conspiracy theory is that it was he who shall not be named, he tricked Donanimhaber and he tricked Chew* and who else will be tricked :sneaky:

Tricked? Then you better watch this video carefully >> Maximum Speed | AMD FX Processor Takes Guinness World Record. You will find Chew* in there.

 

[NostaSeronx]

Tricked? Then you better watch this video carefully >> Maximum Speed | AMD FX Processor Takes Guinness World Record. You will find Chew* in there.

I know who chew* is lol

I visit the XtremeSystem forums every once in awhile and I read his farewell letter on hwbot and xtremesystems forum
http://www.xtremesystems.org/forums/showthread.php?272771-All-things-must-come-to-an-end-eventually

But, still he is dead wrong about 4C/8T and Glew's MCMT doesn't apply to AMD's CMT(The design is a higher revision)

 

[MisterMac]

You have to understand the 512 bit execution* is a special move execution called "Move Elimination"

I like how you said "if" thanks my excuse for lack of FPU performance would be it's biased and not properly compiled/programmed to effectively use performance enhancing features

http://developer.amd.com/tools/lwp/pages/default.aspx
http://www.anandtech.com/show/2302

Should help a lot in programming for parallelism :whiste:

A 256bit Floating Point Execution can occur per cycle, the delay for an average floating point to get scheduled and execute is 12+ cycles so plenty of time for the other cores 256bit Floating Point Execution to occur

Also 256bit Integer executions can occur per cycle as well but the delay for an average integer command to get executed is 5+ cycles
(This is big news for x264 encoders)

I call the executions but the real term is operation

Then listen to what BlueBlazer is saying jesus christ.


Your openly admitting to stretching the definitions of what a traditional core represents.

If intel pushed a itanimum/x68-64 combo and then blamed people for not using instructions and only legacy support - youd be whining just the same.


And now the big bomb - the reason AMD is doign this is to try position itself marketing wise with CORES as a KEY SELLING POINT.

It's not the same a HT, but it's not the same as a core either.
Intel learned that atleast.

AMD is just trying to bloat itself up cause of the massive SERVER losses last 5 years.
And if module design was such an advantage - it'd be out by now, period.

 

[NostaSeronx]

And now the big bomb - the reason AMD is doign this is to try position itself marketing wise with CORES as a KEY SELLING POINT.

It's not the same a HT, but it's not the same as a core either.
Intel learned that atleast.

I don't see that

What is called a integer cluster is what is considered a core in most AMD Processors since K7, so it is the same as a Core

Cores have always been a selling point for AMD

You can only have a processor if it processes data and the cores do that....the functional units do that which happen to be the "Integer Clusters" in this case

Intel can't call HTT cores because it isn't physical reproduction/duplication of the cores it's a virtual duplication...notice AMD is doing physical duplication and Intel is doing virtual duplication

AMD if you check the several pictures I have posted show die shots clearly showing two cores

Intel's cores are naturally big 3 ALUs that are 256bits big(Int and fpInt, fpFP are all processed) and 3 AGUs(2 that store and load/1 that just stores)

The AMD K15h's Compute Unit Microarchitecture can be considered a core if only looking at what Intel does with their cores(AMD does what Intel does but does it Physically)
but we don't look at Intel we look at previous AMD Designs which lead towards the classic definition of a core is where common data gets executed

 

[Idontcare]

Is a 386 CPU a "core"?

What makes a 486 SX any less of a core than a 486 DX?

I don't think we can cleanly define cores on the basis of the presence, or lack thereof, of specific portions of the full complement of the ISA.

 

[NostaSeronx]

Is a 386 CPU a "core"?

No, it's a processor

It comes with a Fetch/Decode on die <-- this isn't part of the core

It comes with a Core on die <-- that is the "core", It is easier just to call it an integer cluster....

^_^

Bulldozer has 4 processors on die....and in each processor there is a fetch/decode, two cores, and a maths coprocessor
See, I'm getting this down

Engineer speak now
Orochi has 4 "Bulldozer" Compute Units....and in each compute unit there is a fetch/decode, two integer clusters, and a floating point coprocessor

Got it down

I don't know how ISA's got brought in determining if it's a core or not but okay

The definition of a processor evolved but the definition of a core hasn't

Okay, now to make since of things

Intel Sandy Bridge-P i7 2600K specifically has 4 processors and in each processor there is a fetch/decode, a core w/HTT, the floating point coprocessor is intergrated into the core
1 CPU -> 4 processors -> 8 logical cores -> 8 threads

AMD Bulldozer-Zambezi FX 8120/8150 specifically has 4 modules/compute units(processors) and in each module/compute unit(processor) there is a fetch/decode, two cores, a floating point coprocessor
1 CPU -> 4 processors -> 8 physical cores -> 8 threads

Can we agree on this?

CPU = Everything on the die, Uncore, Processors, and additives(GPUs)
Processor = A Fetch and Decode(usually individualizes what the processor is) /Infinite amount of Cores/Can have additives(FPUs)
Core = Integer Cluster or where data without additives execute
Threads = What software sees as cores

 

[Rudy Toody]

Back in my day: core referred to memory. As in core-dumps.

 

[NostaSeronx]

Back in my day: core referred to memory. As in core-dumps.

It was called core dump because of the raw information in memory that didn't get processed in the core yet....but oh well

 

[MisterMac]

No, it's a processor

It comes with a Fetch/Decode on die <-- this isn't part of the core

It comes with a Core on die <-- that is the "core", It is easier just to call it an integer cluster....

^_^

Bulldozer has 4 processors on die....and in each processor there is a fetch/decode, two cores, and a maths coprocessor
See, I'm getting this down

Engineer speak now
Orochi has 4 "Bulldozer" Compute Units....and in each compute unit there is a fetch/decode, two integer clusters, and a floating point coprocessor

Got it down

I don't know how ISA's got brought in determining if it's a core or not but okay

The definition of a processor evolved but the definition of a core hasn't

Okay, now to make since of things

Intel Sandy Bridge-P i7 2600K specifically has 4 processors and in each processor there is a fetch/decode, a core w/HTT, the floating point coprocessor is intergrated into the core
1 CPU -> 4 processors -> 8 logical cores -> 8 threads

AMD Bulldozer-Zambezi FX 8120/8150 specifically has 4 modules/compute units(processors) and in each module/compute unit(processor) there is a fetch/decode, two cores, a floating point coprocessor
1 CPU -> 4 processors -> 8 physical cores -> 8 threads

Can we agree on this?

CPU = Everything on the die, Uncore, Processors, and additives(GPUs)
Processor = A Fetch/A Decode/Infinite amount of Cores/Can have additives(FPUs)
Core = Integer Cluster or where data without additives execute
Threads = What software sees as cores

No.

Sandy Bridge 2600k:
1 CPU/1 Processor -> 4 Cores -> 8 Virtual Cores(4 FPU/4 Integer shared) > 8 Threads

Zambezi:
1 CPU/1Processor -> 4 Modules/Cores -> 8 Virtual Cores(4 FPU/8 Integer Shared) > 8 Threads.

On paper Zambezi looks strong with its extra "power" in terms of Integer processing.

When its' design was proposed and perhaps early prototype worked, i'd be jumping the hype wagon like a little bitch - wow what a revolution in potential thread scaling we have here.
(Which many things are pointing to we don't )
But they're ALTERING the "traditional" definition for marketing sake.
If they had balls they'd call it what it is. Windows sees 8 cores, but intel doesn't call them that, no matter what subset of architecture they have.

Furthermore i expect atleast 50&#37;(Should i go with 0.80 X instead?) more performance than SandyBridge if they want to call it an 8 core processor.

I seriously doubt that will happen, but lets see.

If i were AMD with a new design architecture, and in charge of marketing - i wouldn't give my enthuasiast class processors any weakness by hyping up more cores - if i had to chance to beat or near match performance of my competitor.

What happens if it does with 8 cores? - any opposing side will tell their customers:
"Yes well our tech is so good, we need HALF of their cores to beat them".

Your setting yourself up for failure.