jiffylube1024
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- Feb 17, 2002
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I was excited about Hammer, but the whole bankruptcy thing has swayed my interest. Besides he was all downhill after "Can't Touch This" ... um, we're talking about the same Hammer, right?
Originally posted by: MajinVegeta
BuddyAtBzboyz, but how much does the P4 have of the P3?
It can sacle well into the multi Ghz range it has a single pipeline, it is a totally new chip, AMD says hammer is an AXP core with additions AMD has never made its own "NEW" core the athlon was taken fron NextGen when aquired not made by AMD, Also the chip dates back pre-athlon even pre-K6-III. so this chip is looking to be more of a Itanic that cant hold its own.
The K7 core is used up it has no where to scale, and a little IPC room left that hammer takes advantage of.
plus your talking 104mm chip yes smaller than current P4's but on SOI W/ Si-28. while Intel will be running prescott with 1 Meg L2 cache, 4+ ghz and a ALU that if still running 2x the core speed(so it only takes 1 clock for results) will but out 2x the ammount of data they do now(the ALU's will be 32 bits on prescotts not 16 likr on northwoods) not to mention HT, and 23 sq mm smaller.
not a bad setup if you ask me.
Hammer isnt really anything new just a reworked Althon for the 3 or 4 time.
AMD says hammer is an AXP core with additions AMD has never made its own "NEW" core the athlon was taken fron NextGen when aquired not made by AMD, Also the chip dates back pre-athlon even pre-K6-III. so this chip is looking to be more of a Itanic that cant hold its own.
Originally posted by: MajinVegeta
Bransford: its an AXP core with a 3rd FP pipeline and the pipelines have 2 extra stages so hammer will have a 12 stage ALU and 17 stage fpu and an improved TLB. .
Also IF the on die MC is use better latency, but it can be disabled but why when the AXP core is memory senstive to latency?
Its the same core minor changes X86-64 takes 2% of die space the rest is improved TLB predictor, third FP pipeline(that will genrate more heat) and on die northbridge.
PLUS Intels SSE2 but that means AMD should have to put a logo on thier chip Intel Inside.
PLUS Intels SSE2 but that means AMD should have to put a logo on thier chip Intel Inside.
Originally posted by: MajinVegeta
Like this one that show 3 seprate Ht links?
http://www.amd.com/us-en/assets/content_type/DownloadableAssets/MPF_Hammer_Presentation.PDF
oh and HT isnt a FSB because each transaction is put on a list then excuted so it takes even longer to access the DRAM hence 20 Entry MCQ.
So now you graphic card if you use the on die northbridge just like amd paper says its transaction will be queued until a spot opens up for it, and to use the CPU it will have to go to the SRQ.
now when you go to MP sytems it gets even uglier, with DRAM fragmentaion and massice queue delays.
Originally posted by: MajinVegeta
The currently presented Hammer resembles much more a highly tuned version of the Athlon Palomino.
http://www.chip-architect.com/news/2001_10_18_AMD_presents_hammer_at_MPF.html
That is correct. The K7 and K8 share several similarities, but the K8 has been developed independantly from the K7 (not sure where I read that thoughThe Hammer a reworked K7?! The Hammer has some similarity to the Athlon, but they are very different CPU's both physically and electronically.
Originally posted by: MajinVegeta
alexruiz It clearly shows the Intergrated northbridge has 3 Ht links, Page 26. why?
One for the AGP tunnel, 1 incase a MB maker wants to use an off die memory controller and a 3rd incaes they want PCI-X, 3GIO, or RapidIO, along with PCI.
Well, I think it needs to be mentioned that while that HT Link is being linked to the AGP Tunnell, it is also the CPU's only connection to the rest of the system (ie Hard Drives, PCI devices, BIOS, etc). Now I will agree that 3.2GBs both ways is prolly overkill, still, it definately does need a dedicated linkBy the way, I don't see how the AGP needs a dedicated HT channel for the multiprocessor version, the 3 HT tunnels are needed to balance the workload among the CPUs (you don't need special training foto figure that, common sense is enough) By the way, Do you have accurate data of the chip size??? AMD is showing the server version, where size is secondary to reliability.
Originally posted by: MajinVegeta
actually the P4/P5(?) switch will be at about 3.2 Ghz not 3.5Ghz or 4Ghz.
Plus if the K7 scales so well why at the .13 micron process hasnt it hit 2Ghz? come onTbred has been cooked my friend with water cooling only got a 200Mhz OC where he could get a 600 with his Pally core. see at the 130nm level issues because apperant within the core that had to be change to prevent errors, these wernt an issue because 180nm process offered stronger signals due to "bigger wires". now at the 130nm tbred cant scale and thats what hammer is based on the core of the chip is only 10% bigger qutoing AMD that means 40-41 million transistors the rest of the 26 million is northbridge.
The papers are out and they look like itanic sister ship the wanna be olympic