Should I Be Excited About Hammer?

[jiffylube1024]

I was excited about Hammer, but the whole bankruptcy thing has swayed my interest. Besides he was all downhill after "Can't Touch This" ... um, we're talking about the same Hammer, right?

 

[MajinVegeta]

BuddyAtBzboyz, but how much does the P4 have of the P3?

It can sacle well into the multi Ghz range it has a single pipeline, it is a totally new chip, AMD says hammer is an AXP core with additions AMD has never made its own "NEW" core the athlon was taken fron NextGen when aquired not made by AMD, Also the chip dates back pre-athlon even pre-K6-III. so this chip is looking to be more of a Itanic that cant hold its own.

The K7 core is used up it has no where to scale, and a little IPC room left that hammer takes advantage of.

plus your talking 104mm chip yes smaller than current P4's but on SOI W/ Si-28. while Intel will be running prescott with 1 Meg L2 cache, 4+ ghz and a ALU that if still running 2x the core speed(so it only takes 1 clock for results) will but out 2x the ammount of data they do now(the ALU's will be 32 bits on prescotts not 16 likr on northwoods) not to mention HT, and 23 sq mm smaller.

not a bad setup if you ask me.

 

[SickBeast]

wow...sounds like amd is in for some trouble...i had no idea intel had all of that coming. as long as amd still has the best bang for the buck, i'll still be buying their chips.

 

[Rainsford]

Originally posted by: MajinVegeta
BuddyAtBzboyz, but how much does the P4 have of the P3?

It can sacle well into the multi Ghz range it has a single pipeline, it is a totally new chip, AMD says hammer is an AXP core with additions AMD has never made its own "NEW" core the athlon was taken fron NextGen when aquired not made by AMD, Also the chip dates back pre-athlon even pre-K6-III. so this chip is looking to be more of a Itanic that cant hold its own.

The K7 core is used up it has no where to scale, and a little IPC room left that hammer takes advantage of.

plus your talking 104mm chip yes smaller than current P4's but on SOI W/ Si-28. while Intel will be running prescott with 1 Meg L2 cache, 4+ ghz and a ALU that if still running 2x the core speed(so it only takes 1 clock for results) will but out 2x the ammount of data they do now(the ALU's will be 32 bits on prescotts not 16 likr on northwoods) not to mention HT, and 23 sq mm smaller.

not a bad setup if you ask me.

Sure, Intel sounds like it's got some good stuff, but you're not backing up anything you say. All you keep repeating is that Hammer will be basically an Athlon with no supporting information or links (not to mention all the information that this is a new core, hence the K8 designation) and then listing all of Prescott's improvements. Sure, Prescott will be better, but that information is meaningless without competing information from AMD, which you don't seem to have. If you have some real info, I'd love to hear it.

 

[MajinVegeta]

Bransford: its an AXP core with a 3rd FP pipeline and the pipelines have 2 extra stages so hammer will have a 12 stage ALU and 17 stage fpu and an improved TLB. .

Also IF the on die MC is use better latency, but it can be disabled but why when the AXP core is memory senstive to latency?

Its the same core minor changes X86-64 takes 2% of die space the rest is improved TLB predictor, third FP pipeline(that will genrate more heat) and on die northbridge.

PLUS Intels SSE2 but that means AMD should have to put a logo on thier chip Intel Inside.

 

[JoeTheHobo]

Hammer isnt really anything new just a reworked Althon for the 3 or 4 time.

AMD says hammer is an AXP core with additions AMD has never made its own "NEW" core the athlon was taken fron NextGen when aquired not made by AMD, Also the chip dates back pre-athlon even pre-K6-III. so this chip is looking to be more of a Itanic that cant hold its own.

I am sorry, I usually try to stay polite, but sometimes I can't help it when trolls are involved.

Hahahahahahahahahahahahahaha!!!

Oh boy, that is so stupid. By your logic the P4 is just a P3 with sh!t smeared on it, or the 486 was just a slightly reworked 8086. I bet you are "teh king of da procesars!!!1!" at your school, huh? Where, exactly, did you get your multiple engineering degrees, Prescott boy?

Then, of course, you like to rant about AMD relabeling cores with slight improvements, but completely ignore the P2 to P3 transition where the P3 at the time was just a P2 with SSE and the oft-ridiculed processor identification number. That was even less of a difference than the one between the K6-II and K6-III, and is nothing compared to the changes between the Athlon and Hammer, which are dramatically different to anyone that knows about processor design, unless you go to "procesar schol numbar#1 !!!" I guess it is really easy to just add some stages to the pipeline, huh? You do know there is no plumbing involved here, right?

Well, that was really fun but I am not going to waste my time responding any further to you. I don't want to hijack the thread, but I think Mr. Prescott Troll Boy did that already.

 

[Rainsford]

Originally posted by: MajinVegeta
Bransford: its an AXP core with a 3rd FP pipeline and the pipelines have 2 extra stages so hammer will have a 12 stage ALU and 17 stage fpu and an improved TLB. .

Also IF the on die MC is use better latency, but it can be disabled but why when the AXP core is memory senstive to latency?

Its the same core minor changes X86-64 takes 2% of die space the rest is improved TLB predictor, third FP pipeline(that will genrate more heat) and on die northbridge.

PLUS Intels SSE2 but that means AMD should have to put a logo on thier chip Intel Inside.

I'm a little confused on why this means the Hammer is a slightly reworked AXP, but even if it is, I'm fine with that as long as it is a fast CPU that isn't too expensive. We'll see what happens when it comes out, but right now I don't think there is enough information to be bashing Hammer (or Prescott for that matter).

Uh...dude..."Bransford"?

 

[SickBeast]

the hammer is NOT a reworked athlon xp. you guys don't know what you're talking about.

 

[BuddyAtBzboyz]

PLUS Intels SSE2 but that means AMD should have to put a logo on thier chip Intel Inside.

Just like any Intel product that uses hypertransport should be labelled "AMD inside". Seriously if you have real information feel free to share it but try to remain objective man.

 

[MajinVegeta]

Joe:but completely ignore the P2 to P3 transition where the P3 at the time was just a P2 with SSE and the oft-ridiculed processor identification number.

you forgot to mention the full speed cache, going from non blocking 512Mb or 4 Gb cacheable to non blocking 64 Gb cacheable. Plus the read and write buffers was shared in the P3 4x 32 read/write V the P2 4 X 32 read and 32 write.

Plus the P3 droped the TagRAM plus 4x 32kx32.

so ya there was a difference.

Budd: If intel puts it on die or Intel chipset yes if the chipset makers such as SiS or Via puts it on the chipset for features, No.

Rainsford sorry about mis typing your name.

 

[AthlonRaider]

The PIII debuted with off-die 512k L2 cache in the Slot 1 cartridge package, which was the same as the PII.

BTW: Hammer will also have 6 integer pipes vs only 3 for K7.

 

[MajinVegeta]

Joe: also the P4 is a totaly different beast single 20 stage pipeline. REE, and other features greatly seprate it from the P3.

AMD has alwasy tried to make a chip last longer than it was designed to remember when AMD said there was no need for a 386 becuase they added Mhz to the 286?

there claim better clock for clock performance, and who squashed them like the pest they were back then.

The currently presented Hammer resembles much more a highly tuned version of the Athlon Palomino.
http://www.chip-architect.com/news/2001_10_18_AMD_presents_hammer_at_MPF.html

 

[alexruiz]

Originally posted by: MajinVegeta
Like this one that show 3 seprate Ht links?
http://www.amd.com/us-en/assets/content_type/DownloadableAssets/MPF_Hammer_Presentation.PDF

oh and HT isnt a FSB because each transaction is put on a list then excuted so it takes even longer to access the DRAM hence 20 Entry MCQ.

So now you graphic card if you use the on die northbridge just like amd paper says its transaction will be queued until a spot opens up for it, and to use the CPU it will have to go to the SRQ.

now when you go to MP sytems it gets even uglier, with DRAM fragmentaion and massice queue delays.

Yeah, like that one.... Ooops, you got the one that is for the sledgehammer. The clawhammer has only ONE HT link.

 

[mechBgon]

Originally posted by: MajinVegeta

The currently presented Hammer resembles much more a highly tuned version of the Athlon Palomino.
http://www.chip-architect.com/news/2001_10_18_AMD_presents_hammer_at_MPF.html

I don't care if Hammer is a highly-tuned Palomino, a highly-tuned Cyrix or a highly-tuned fudge brownie... as long as it performs well for a reasonable price, I'm going to give it my consideration. Isn't that what counts?

 

[MajinVegeta]

alexruiz It clearly shows the Intergrated northbridge has 3 Ht links, Page 26. why?

One for the AGP tunnel, 1 incase a MB maker wants to use an off die memory controller and a 3rd incaes they want PCI-X, 3GIO, or RapidIO, along with PCI.

 

[Vic]

Ugh... I hate fanboys. :|

Look, the reality is that no one outside of AMD knows what the Hammer is going to be like or how it will perform. Yes, AMD did reveal a brief white paper and presentation, but no specifics and no performance figures have been revealed, nor are they likely to reveal anything until shortly before the launch.

Basing your information and speculating from websites that are doing nothing more than speculating themselves from the thousands of patents that AMD has filed in the last couple of years is pure stupidity. Comparing a possible product that AMD has not revealed or released against a possible product that Intel has not yet revealed or released is even stupider. I can see that you have made this your life, MajinVegeta, but I got bad news for you. We simply won't know until they are released and they are benchmarked side-by-side. Until then, it's all speculation and bullsh!t.

As the K8 merely being a re-vamped K7, would there be something wrong with that? Was there anything wrong with the K7, a product that had Intel beat and playing catch-up for 2 years?? You claim the K7 has scaled all the way, and so that means the K8 will not scale. Where's the logic in that? Even if that were true, which I doubt, perhaps that's why AMD is focusing on 64-bit and IPC efficiency? As a (relatively poor) analogy, an 8.0L Viper V-10 engine at 2,500rpm is a hell of a lot more powerful than a 1.6L Civic Si engine at 8,000rpm. MHz ain't everything.

Also, you act as though the P4 will scale indefinitely. I beg to differ. On 0.13u, I give the P4 only until 3.5GHz (I base this information off the fact that, whenever Intel debuts a new design, they always demo it as some "amazing" speed and that speed ALWAYS ends up being the final scale of that design), then Intel will have problems. So they go Prescott and 0.09u and they scale forever, right? Wrong. Already, we are seeing reliability problems with P4's because of small gate size, and that is a problem that will only get worse at 0.09u. Too bad Intel couldn't see the logic in paying IBM to license SOI, eh?

In the end though, all of this is mental masturbation. We'll know when the products are released, we'll know when we see the benchmarks, we'll know when we have them in our systems. Not before.

Personally, though, I am very excited to see the Hammer come out. 64-bit is the future, and I think it's long overdue. I hope it kicks major a$$, and then I really look forward to seeing what Intel launches in return. It's the competition that drives all this, and what makes it all so fun and exciting.

 

[MajinVegeta]

actually the P4/P5(?) switch will be at about 3.2 Ghz not 3.5Ghz or 4Ghz.

Plus if the K7 scales so well why at the .13 micron process hasnt it hit 2Ghz? come onTbred has been cooked my friend with water cooling only got a 200Mhz OC where he could get a 600 with his Pally core. see at the 130nm level issues because apperant within the core that had to be change to prevent errors, these wernt an issue because 180nm process offered stronger signals due to "bigger wires". now at the 130nm tbred cant scale and thats what hammer is based on the core of the chip is only 10% bigger qutoing AMD that means 40-41 million transistors the rest of the 26 million is northbridge.

The papers are out and they look like itanic sister ship the wanna be olympic

 

[SickBeast]

OK, I'm no expert here, but doesn't more transistors generally translate to higher performance? If that's the case, the 41 million gates on the hammer sounds puny. The R9700 that ATI just announced has 107 million transistors, and it's built on 0.15 microns. And why did AMD decide to integrate the northbridge into the chip? Just to avoid VIA making another piece of junk that will cause systems to crash? Will it somehow boost performance in any way? IMHO I think AMD should have just crammed a ton of transistors onto the chip and left the northbridge to the chipset makers. We'll have to wait and see about the performance, but if I owned AMD stock right now I would be selling. By the way, 41 million transistors sounds like WAY too little for a chip with 512kb of L2 cache and a built-in northbridge.

 

[r0ck]

all i know is my XP 2100+ beats P4 2.4Ghz for less than half the price
and most likely hammer will kick some major a$$

 

[DeepBlueJH]

yeah... in like 20% of the benchmarks run on the processors..

yah! for shameless bias

 

[BlvdKing]

MajinVegeta is known to spread FUD and disinformation about AMD in every one of his posts.

The Hammer a reworked K7?! The Hammer has some similarity to the Athlon, but they are very different CPU's both physically and electronically.

Deeper registers, x86-64, onboard memory controller, SSE2, more cache (512K or more), longer pipeline for higher MHz are just some of the improvements. A totally different motherboard design, a new socket (with a HS/fan mechanism clipping mechanism that is superior to the P4), stainless steel heatspreader, SOI .13 micron fabrication process, and improved thermal protection are some physical improvements.

Why do you insult our intelligence with your disinformation about AMD's products? The Hammer is not an Athlon with more cache like the K6-3 was to the K6-2. Stop spreading lies.

 

[Athlon4all]

The Hammer a reworked K7?! The Hammer has some similarity to the Athlon, but they are very different CPU's both physically and electronically.

That is correct. The K7 and K8 share several similarities, but the K8 has been developed independantly from the K7 (not sure where I read that though

 

[alexruiz]

Originally posted by: MajinVegeta
alexruiz It clearly shows the Intergrated northbridge has 3 Ht links, Page 26. why?

One for the AGP tunnel, 1 incase a MB maker wants to use an off die memory controller and a 3rd incaes they want PCI-X, 3GIO, or RapidIO, along with PCI.

Yes, it says 3, but that is the sledgehammer. The clawhammer has ONLy one (check vanshardware.com info abuit it).

By the way, I don't see how the AGP needs a dedicated HT channel for the multiprocessor version, the 3 HT tunnels are needed to balance the workload among the CPUs (you don't need special training foto figure that, common sense is enough) By the way, Do you have accurate data of the chip size??? AMD is showing the server version, where size is secondary to reliability.

I keep thinking there is much more than what we think..... those 2000 patents in 2 years (80% for the K8) keep spinning in my head, specially when some of them were about dual cores..... I would be extremely glad to confirm it.

 

[Athlon4all]

By the way, I don't see how the AGP needs a dedicated HT channel for the multiprocessor version, the 3 HT tunnels are needed to balance the workload among the CPUs (you don't need special training foto figure that, common sense is enough) By the way, Do you have accurate data of the chip size??? AMD is showing the server version, where size is secondary to reliability.

Well, I think it needs to be mentioned that while that HT Link is being linked to the AGP Tunnell, it is also the CPU's only connection to the rest of the system (ie Hard Drives, PCI devices, BIOS, etc). Now I will agree that 3.2GBs both ways is prolly overkill, still, it definately does need a dedicated link

 

[Vic]

Originally posted by: MajinVegeta
actually the P4/P5(?) switch will be at about 3.2 Ghz not 3.5Ghz or 4Ghz.

Plus if the K7 scales so well why at the .13 micron process hasnt it hit 2Ghz? come onTbred has been cooked my friend with water cooling only got a 200Mhz OC where he could get a 600 with his Pally core. see at the 130nm level issues because apperant within the core that had to be change to prevent errors, these wernt an issue because 180nm process offered stronger signals due to "bigger wires". now at the 130nm tbred cant scale and thats what hammer is based on the core of the chip is only 10% bigger qutoing AMD that means 40-41 million transistors the rest of the 26 million is northbridge.

The papers are out and they look like itanic sister ship the wanna be olympic

Wow, you sure do know how to spead the FUD, dontcha?

:disgust:

First, the Tbred is still developing and OC'es are beginning to improve. Perhaps you forget that the original P4 Willamette couldn't OC for sh!t? Anyway, the Tbred's current and real problems of scalability, which you completely ignore, are caused by (1) small die size which decreases the efficiency of heat dissapation, and (2) current leakage at the gates on the 0.13u die (a problem which the P4 is beginning to experience as well and will only get worse as Intel scales that design smaller). Both of these problems are completely addressed with the Hammer, the first with 512KB L2 cache and on-die memory controller which will increase the size of the core greatly while still using a 0.13u die or smaller, thus providing more surface contact area for thermal dissipation, and the second with SOI. If you don't understand the potential of SOI, I strongly suggest you read IBM's white paper on their clever invention. It owns Intel.

Second, there is no way that Hammer is only 40-41M transistors. I don't know where you read that BS and don't care. My Palomino is 37.5M transistors and there is no way that AMD included SSE2, 64-bit, a deeper pipeline, a larger cache, AND the memory controller by only increasing the transistor count by ~3M. You have no idea how stupid you sound.

Third, which brings me to my last point. I don't like to play the grammar nazi, but you write and spell like a 12-year-old who doesn't get good grades. You use run-on sentences and can't construct a coherent verbal structure, much less a valid argument based on researched and documented facts. And yet you expect the rest of us to believe that you know something about state-of-the-art microchip architecture?? Spread that FUD elsewhere, boy.