Should I Be Excited About Hammer?

[MajinVegeta]

me spreading FUD I am quoting AMD's white papers how is that FUD?

your the one who is spreading FUD Clawhammer wont have 512K L2 cache. 2% of die space is x86-64, they are op code not a full instruction set hence it is like Intels MMX/SSE/SSE2. SSE2 accounts for only 2% of the new core space, piplines, are tiny, so are op codes. cache, and decoding units is the bulk of the transistor in a chip.

AXP are current 15 million transistors are L2 cache, and antoher 8 million for the L1 (it takes more for L1 due to the lower latency and higher speeds) thats 23 million transistor out of 37.5, 14.5 million are the actaul core and most of that is the decoder for the X86 instructions, The rest of the chip is very small.

maybe a little more research would help you understand what the core is made of and how it works. Take the P4 for example, 26 million of its transisotr are L2 cache 2 million are L1. That leaves 27 million 1/2 of them are for the decoding units for when HT is enabled a that leaves 13 million almost the same size as the AXP.

 

[Rainsford]

Originally posted by: MajinVegeta
me spreading FUD I am quoting AMD's white papers how is that FUD?

your the one who is spreading FUD Clawhammer wont have 512K L2 cache. 2% of die space is x86-64, they are op code not a full instruction set hence it is like Intels MMX/SSE/SSE2. SSE2 accounts for only 2% of the new core space, piplines, are tiny, so are op codes. cache, and decoding units is the bulk of the transistor in a chip.

AXP are current 15 million transistors are L2 cache, and antoher 8 million for the L1 (it takes more for L1 due to the lower latency and higher speeds) thats 23 million transistor out of 37.5, 14.5 million are the actaul core and most of that is the decoder for the X86 instructions, The rest of the chip is very small.

maybe a little more research would help you understand what the core is made of and how it works. Take the P4 for example, 26 million of its transisotr are L2 cache 2 million are L1. That leaves 27 million 1/2 of them are for the decoding units for when HT is enabled a that leaves 13 million almost the same size as the AXP.

Well you do sound like you have a whole lot of numbers there. But like I've said before, I plan on waiting for Hammer to actually come out before posting about how good/bad it is. I think you're jumping the gun here. And I still think (your huge mass of numbers not withstanding) that anyone with half a brain can tell the Hammer is not just a slightly reworked Athlon. Of course I'm only in my first year of Computer Engineering, so I don't know the ins and outs of CPU design, but I sure as hell know that the features of the Hammer make it very different from the Athlon. And even if it turns out to be pretty much an Athlon with a few features slapped on, so what? I care about performance, stability and price. AMD has always delivered all three for me and if Hammer continues that tradition I'll be happy regardless of how many transistors it has.

Um, and if you want to improve your credability, learn how to write and spell. Unless English is not your first language, then disregard this. But you don't sound very smart when you post sentences without the use of periods.

 

[mechBgon]

Now, don't be so hard on him for his punctuation; maybe he ran out of periods, commas and hyphens, and only has letters and numerals left. Anyone got some extras you can lend him? I guess can spare a few, here we go:

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That should get him by for a few posts, anyway. Those ones come from a Duron-based system, so I don't know how well they'll work on his Intel rig, but it's all I've got right now. If I run out of (ahem) numbers, I'll expect him to return the favor.

 

[imgod2u]

Ok, a few things to correct here. First and foremost, the Athlon already has 3 FP pipelines. K8 will not add more pipelines. It will add 2 stages to both the integer and FP pipeline. These stages aren't just breaking up previous stages into simpler stages in order to help scalability (like the case on the P6 to P7 core transition). These stages actually add new processes. The new packing stage will allow more efficient use of the execution units. Then there's the integrated memory controller, the x86-64 extensions and improved caching. The basics of the core is pretty much the same. Certain not as dramatic a change as the P6 to P7 core change. But technically, it is a new core. Although most of it is the same as the Athlon, save the additions I made above.