Skylake/Broadwell Roadmap Update @Vr-zone

[DrMrLordX]

I'd love to see AVX512 go mainstream, but we have so little support for AVX/AVX2 right now that it almost makes no sense to push it out to the consumer market.

Even supporting AVX/AVX2 isn't so simple as flipping a switch. Based on my very limited experience, you've got to at least have blocks of instructions involving 512 bits of operands (to fill two 256-bit registers) being acted upon by like operators. There may be enough flexibility with AVX and/or AVX2 that the operators need not be uniform (FMA?), but frankly I don't know enough about the instruction set to say so for sure. You can also have less than 512 bits of data, but you're basically losing performance since AVX/AVX2 lets you complete the operation on all the data loaded into the registers at once, so you may as well fill them up if you can.

Anyway, if your code is too branchy or if there's too much dependance on prior operations to run your block of code in parallel, it can screw up AVX/AVX2 and all other sorts of SIMD operations as well.

AVX512 seems to extend the length of AVX registers to 512 bits (among other things), so you'd actually want/need 1024 bits of operands in parallel to take full advantage of that feature.

 

[NTMBK]

AVX-512 doubles the size of the vector registers and also doubles the number of vector registers. (There's a total of 2KB of register space!) Oh, and it adds 8 new mask registers too. It's a big upgrade.

 

[Nothingness]

AVX-512 doubles the size of the vector registers and also doubles the number of vector registers. (There's a total of 2KB of register space!)

With support for renaming you can at the very least double that 2KB

Oh, and it adds 8 new mask registers too. It's a big upgrade.

And Intel will make sure it won't be widely supported before long thanks to market segmentation, though in that case it can be argued that having AVX-512 on mobile chips at 14nm really makes little sense. It would have been nice to at least get it on non Xeon desktop variants

 

[DrMrLordX]

(There's a total of 2KB of register space!)

With support for renaming you can at the very least double that 2KB

Okay, so 4096 bits rather than 1024 bits, if not more . . . oof!

 

[seitur]

Like AVX2 there is almost no productive application available for consumers. It mainly helped stress tester like Prime95, for Intel this was a disadvantage for Haswell in many temperature and power tests. And by the way it is Intel who confirmed that AVX-512 is Xeon only.

There is almost no productive aplications for consumers using new instruction sets because there is very little CPUs that have those instuction sets.

Put those new instructuion sets in all big core Intel CPUs - from Celeron&Pentium up to Xeons and you'll have software using those instructions earlier.

Software developers are not gonna code their general population aplications to use AVX2/AVX-512/TSX, etc if there is very little users having hardware capable of using them.

Hardware have to come first, software comes second. That is how it works.

 

[kimmel]

Because they both SHARE the same micro architecture ?

It makes no sense to disable a perfectly functional part of a chip ...

Again with assuming that the die won't be physically different. They aren't disabling anything. It won't be physically present. There is nothing to disable.

There's more to gain by keeping that extension in the consumer versions than disabling it ...

Consumers having AVX 512 capable CPUs translates to programmers actively seeking out to support it since it is a key enabler to unlocking more performance and not only that but it can also increase revenue too because there would be more incentives to buy a CPU that supports that extension so it's a win-win scenario all around ...

I think Intel sees that consumers want low power low cost devices. So from their perspective why spend additional die space that both costs more money and power when those are not your customers primary purchasing decisions. The consumer core part is for 5w tablets first and other parts later. Do the benefits outweigh the cost for AVX-512 on a 5w tablet part? I am not positive that is true.

Yes it hampers adoption of those instructions, but so does not being able to sell your chip into a tablet or eventually into a cheap phone.

 

[Nothingness]

I think Intel sees that consumers want low power low cost devices. So from their perspective why spend additional die space that both costs more money and power when those are not your customers primary purchasing decisions. The consumer core part is for 5w tablets first and other parts later. Do the benefits outweigh the cost for AVX-512 on a 5w tablet part? I am not positive that is true.

Do you really think current Core-based Celeron and Pentium chips don't have AVX2 on-chip? I'm convinced they have it, it's just fused off.

Silvermont is another different story (and not the subject of this thread).

 

[kimmel]

Do you really think current Core-based Celeron and Pentium chips don't have AVX2 on-chip? I'm convinced they have it, it's just fused off.

Silvermont is another different story (and not the subject of this thread).

I think past performance is not always an indicator of future performance. I also think that most features don't suck the die space or power like AVX-512 probably will. Also, AVX2 was architected in a very different world than we live in now.

 

[beginner99]

wccftech...
Intel Preparing Something ‘Big’ and ‘Disruptive’ with Skylake Microarchitecture

Sounds cool but you must be insane intel would introduce this using the mainstream CPU uArch. If they would do such a drastic change it would probably first be with a low volume specialized server chip and see how it goes and sells.

 

[witeken]

Sounds cool but you must be insane intel would introduce this using the mainstream CPU uArch. If they would do such a drastic change it would probably first be with a low volume specialized server chip and see how it goes and sells.

Why? If the chip works as it is designed, which is for higher performance per clock within a given die area and power constraint, than why should a new architecture feature remain exclusive for -- well, Intel recycles its architecture from 3.5W to 140W, so I'm not sure which kind of chip you mean, since they're all Core?

 

[DrMrLordX]

Do you really think current Core-based Celeron and Pentium chips don't have AVX2 on-chip? I'm convinced they have it, it's just fused off.

Silvermont is another different story (and not the subject of this thread).

Allegedly, Silvermont supports pretty much every extension in the flagship Haswell parts (AVX2 etc). Airmont, which is the basis for Knight's Landing, will support AVX-512.

And you're right, the low-end Haswells probably DO support those instructions. They're just disabled. My guess is some penny-pincher was afraid that an AVX2-enabled Pentium could go so fast with AVX2 code that nobody would want/need a quad on the low-to-mid end. Or something.

 

[mikk]

Allegedly, Silvermont supports pretty much every extension in the flagship Haswell parts (AVX2 etc). Airmont, which is the basis for Knight's Landing, will support AVX-512

Just wrong. Silvermont doesn't support AVX, Airmont won't do either. Also Knights Landing will get enhanced Silvermont cores not Airmont.

 

[jdubs03]

Just wrong. Silvermont doesn't support AVX, Airmont won't do either. Also Knights Landing will get enhanced Silvermont cores not Airmont.

I think KL will get Airmont, as most people reference it as just a die-shrink of silvermont.

 

[mikk]

Intel himself confirmed that KNL is based on enhanced Silvermont.

 

[jdubs03]

Indeed this is pretty much it:

 

[Ajay]

Well, from the ISSCC preview article on the AT front page - I think SKL will need to deliver a very substantial improvement in IPC in order to best Haswell's throughput.

At 14nm it represents a doubling of the density at 14.5 Mb per square millimeter, but also provides substantially lower minimum voltage for a given frequency compared to the previous 22nm process. As shown in the graph in the slide, 0.6V is good for 1.5 GHz, but it can scale up to 3 GHz. It is also worth noting that the 14nm yield gradient is more conducive to lower voltage operation compared to the 22nm process.

It sounds like the frequency vs Vdd curve is likely to be even flatter than it was for 22nm. In that case, "Big and Disruptive" could be a substantial increase in IPC (and how that is achieved). Kind of useless speculation based on so little information, but I'd thought I throw it out there anyway.

Of course, there have been rumors that 14nm will deliver faster xtor switching speeds - maybe ISSCC will clear up some of these questions.

 

[beginner99]

Why? If the chip works as it is designed, which is for higher performance per clock within a given die area and power constraint, than why should a new architecture feature remain exclusive for -- well, Intel recycles its architecture from 3.5W to 140W, so I'm not sure which kind of chip you mean, since they're all Core?

My point was if there is a single critical issue in such a new design it would affect notebooks up to servers for at least a whole generation. Not a risk a sane company would take.

Keep in mind when core2 was introduced it wasn't new at all. It was based on mobile chips (core uArch) which were based on AFAIK Pentium pro. There wasn't anything that fundamentally new in them like MorphCore. The time intel came up with an actual new uArch was Netburst and we all know how well that went. It was worse than their previous chips at first.

EDIT:

And given the current situation Intel doesn't need to take risks. It is the underdogs that must do so.

 

[DrMrLordX]

Just wrong. Silvermont doesn't support AVX, Airmont won't do either. Also Knights Landing will get enhanced Silvermont cores not Airmont.

Intel himself confirmed that KNL is based on enhanced Silvermont.

So what, do you mean Wikipedia has something on it that is incorrect? Unheard-of! But hey, fortunately, I double-checked Silvermont in the form of the Z3770 which, according to many sources, does not have AVX. ARK doesn't list it at all under the Z3770 which is a pretty good indicator that the instruction set is not present.

So will the "enhanced Silvermont" that others seem intent upon calling Airmont be produced in 14nm or 22nm?

In any case, Knight's Landing will be sold in a market segment where AVX512 support will be both appreciated and used. Low-end Skylake . . . maybe not so much.

 

[witeken]

So will the "enhanced Silvermont" that others seem intent upon calling Airmont be produced in 14nm or 22nm?

Knights Landing architecture is Silvermont with appropriate modifications, shrunk to 14nm.

 

[Ajay]

The are a couple of good articles about KNL on RWT. This one is more of an updated summary: http://www.realworldtech.com/knights-landing-details

 

[Phynaz]

David Kanter hypothesizes that Skylake will not use a ring interconnect and will use a mesh fabric instead.

Interesting change if true.